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Kamalaksha Baral

Observed names: K Baral, K. Baral, Kamlaksha Baral
ORCID: 0000-0001-8546-8021
Observed ORCID: 0000-0001-8546-8021
OpenAlex ID: A5032132062
Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications
2020 · Manas Ranjan Tripathy, Ashish Kumar Singh, et al. · IEEE Transactions on Electron Devices · 193
2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure
2017 · Sanjay Kumar, Ekta Goel, et al. · IEEE Transactions on Electron Devices · 188
III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications
2020 · Manas Ranjan Tripathy, Ashish Kumar Singh, et al. · Superlattices and Microstructures · 76
2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure
2017 · Sanjay Kumar, Kunal Singh, et al. · IEEE Transactions on Electron Devices · 76
Temperature analysis of Ge/Si heterojunction SOI-Tunnel FET
2017 · Sweta Chander, Sanjeet Kumar Sinha, et al. · Superlattices and Microstructures · 65
Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide
2021 · Manas Ranjan Tripathy, A. Samad, et al. · Microelectronics Reliability · 54
GaSb/GaAs Type-II Heterojunction TFET on SELBOX Substrate for Dielectric Modulated Label-Free Biosensing Application
2022 · Ashish Kumar Singh, Manas Ranjan Tripathy, et al. · IEEE Transactions on Electron Devices · 53
Simulation Study and Comparative Analysis of Some TFET Structures with a Novel Partial-Ground-Plane (PGP) Based TFET on SELBOX Structure
2019 · Ashish Kumar Singh, Manas Ranjan Tripathy, et al. · Silicon · 44
Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs
2019 · S. Chander, S. Baishya, et al. · Superlattices and Microstructures · 43
Investigation of DC, RF and linearity performances of a back-gated (BG) heterojunction (HJ) TFET-on-selbox-substrate (STFET): Introduction to a BG-HJ-STEFT based CMOS inverter
2020 · Ashish Kumar Singh, Manas Ranjan Tripathy, et al. · Microelectronics Journal · 42
Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET
2020 · Manas Ranjan Tripathy, Ashish Kumar Singh, et al. · Semiconductor Science and Technology · 36
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Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate
2020 · Ashish Kumar Singh, Manas Ranjan Tripathy, et al. · Applied Physics A · 35
Comparative Analysis and Performance Optimization of Low-Cost Solution-Processed Hybrid Perovskite-Based Solar Cells With Different Organic HTLs
2022 · Deepak Kumar Jarwal, Chandani Dubey, et al. · IEEE Transactions on Electron Devices · 29
Deep Insight into DC/RF and Linearity Parameters of a Novel Back Gated Ferroelectric TFET on SELBOX Substrate for Ultra Low Power Applications
2020 · Ashish Kumar Singh, Manas Ranjan Tripathy, et al. · Silicon · 27
Design and Performance Assessment of HfO2/SiO2 Gate Stacked Ge/Si Heterojunction TFET on SELBOX Substrate (GSHJ-STFET)
2022 · Ashish Kumar Singh, Manas Ranjan Tripathy, et al. · Silicon · 24
Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis
2020 · Prince Kumar Singh, Kamalaksha Baral, et al. · Applied Physics A · 19
2-D analytical modeling of drain and gate-leakage currents of cylindrical gate asymmetric halo doped dual material-junctionless accumulation mode MOSFET
2020 · Kamalaksha Baral, Prince Kumar Singh, et al. · AEU - International Journal of Electronics and Communications · 19
Performance Optimization of ZnO Nanorods ETL Based Hybrid Perovskite Solar Cells With Different Seed Layers
2022 · Deepak Kumar Jarwal, Ashwini Kumar Mishra, et al. · IEEE Transactions on Electron Devices · 18
Performance Comparison of Ge/Si Hetero-Junction Vertical Tunnel FET with and Without Gate-Drain Underlapped Structure with Application to Digital Inverter
2020 · Manas R. Tripathy, Ashish K. Singh, et al. · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · 15
Device-Level Performance Comparison of Some Pocket Engineered III-V/Si Hetero-Junction Vertical Tunnel Field Effect Transistor
2020 · Manas Ranjan Tripathy, Ashish Kumar Singh, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 15
Ultrathin body nanowire hetero-dielectric stacked asymmetric halo doped junctionless accumulation mode MOSFET for enhanced electrical characteristics and negative bias stability
2019 · Kamalaksha Baral, Prince Kumar Singh, et al. · Superlattices and Microstructures · 11
Analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel FETs with oxide interface charge
2019 · P K Singh, K Baral, et al. · Indian Journal of Physics · 11
Ferroelectric Gate Heterojunction TFET on Selective Buried Oxide (SELBOX) Substrate for Distortionless and Low Power Applications
2020 · Ashish Kumar Singh, Manas Ranjan Tripathy, et al. · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · 10
Device and Circuit-Level Performance Comparison of Vertically Grown All-Si and Ge/Si Hetero-Junction TFET
2020 · Manas Ranjan Tripathy, A Samad, et al. · IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) · 9
Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO2/HfO2 Cylindrical Gate TFETs
2020 · Prince Kumar Singh, Kamalaksha Baral, et al. · Silicon · 8
Works count: 52
Citation count: 1,192
H-index: 18
I10-index: 23
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