Get started
Author

Hasan Hassan

Observed name: Hassan, Hasan
Institution: ETH Zurich
ORCID: 0000-0001-9766-007X
Observed ORCID: 0000-0001-9766-007X
OpenAlex ID: A5032313427
Ambit
2017 · Vivek Seshadri, Donghyuk Lee, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 450
TRRespass: Exploiting the Many Sides of Target Row Refresh
2020 · Pietro Frigo, Emanuele Vannacc, et al. · IEEE Symposium on Security and Privacy (S&P) · 227
PDF
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques
2020 · Jeremie S. Kim, Minesh Patel, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 180
PDF
ChargeCache: Reducing DRAM latency by exploiting row access locality
2016 · Hasan Hassan, Gennady Pekhimenko, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 166
LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory
2016 · Amirali Boroumand, Saugata Ghose, et al. · IEEE Computer Architecture Letters · 161
Understanding Latency Variation in Modern DRAM Chips
2016 · Kevin K. Chang, Abhijith Kashyap, et al. · ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS) · 158
GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies
2018 · Jeremie S. Kim, Damla Senol Cali, et al. · BMC Genomics · 149
PDF
GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies
2018 · Kim, Jeremie S., Cali, Damla S., et al. · Repository for Publications and Research Data (ETH Zurich) · 146
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices
2018 · Jeremie S. Kim, Minesh Patel, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 141
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows
2021 · A. Giray Yaglikci, Minesh Patel, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 135
PDF
Understanding Reduced-Voltage Operation in Modern DRAM Devices
2017 · Kevin K. Chang, Abdullah Giray Yağlıkçı, et al. · ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS) · 124
SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies
2017 · Hasan Hassan, Nandita Vijaykumar, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 124
GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping
2017 · Mohammed Alser, Hasan Hassan, et al. · Bioinformatics · 110
PDF
CoNDA
2019 · Amirali Boroumand, Saugata Ghose, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 100
Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications
2021 · Hasan Hassan, Yahya Can Tugrul, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 97
PDF
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput
2019 · Jeremie S. Kim, Minesh Patel, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 94
PDF
CROW
2019 · Hasan Hassan, Minesh Patel, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 86
Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM
2016 · Seshadri, Vivek, Lee, Donghyuk, et al. · arXiv (Cornell University) · 85
PDF
A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses
2021 · Lois Orosa, Abdullah Giray Yaglikci, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 82
PDF
Shouji: a fast and efficient pre-alignment filter for sequence alignment
2019 · Mohammed Alser, Hasan Hassan, et al. · Bioinformatics · 82
PDF
Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines
2018 · Jeremie Kim, Minesh Patel, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 73
What Your DRAM Power Models Are Not Telling You
2018 · Saugata Ghose, Abdullah Giray Yaglikçi, et al. · ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS) · 69
DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips
2023 · Ataberk Olgun, Hasan Hassan, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 68
PDF
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off
2020 · Haocong Luo, Taha Shahroodi, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 67
PDF
Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices
2019 · Minesh Patel, Jeremie S. Kim, et al. · International Conference on Dependable Systems & Networks/Proceedings · 67
Works count: 64
Citation count: 4,009
H-index: 35
I10-index: 48
Year
Topic
Type