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Shivendra Singh Parihar
Observed names:
Parihar, Shivendra Singh,
S. S. Parihar,
Shivendra S Parihar,
Shivendra S. Parihar
Observed institutions:
University of Stuttgart,
Shri Govindram Seksaria Institute of Technology and Science,
Indian Institute of Technology Delhi,
Indian Institute of Technology Kanpur,
University of California, Berkeley
ORCID:
0000-0001-7104-2396
Observed ORCID:
0000-0001-7104-2396
OpenAlex ID:
A5032329214
BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs
2020
·
Avirup Dasgupta
, Shivendra Singh Parihar
, et al.
·
IEEE Transactions on Electron Devices
·
70
Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET
2018
·
R. Singh
, K. Aditya
, et al.
·
IEEE Electron Device Letters
·
66
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K
2023
·
Shivendra Singh Parihar
, Victor M. van Santen
, et al.
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
45
Compact Model for Geometry Dependent Mobility in Nanosheet FETs
2020
·
Avirup Dasgupta
, Shivendra Singh Parihar
, et al.
·
IEEE Electron Device Letters
·
38
Cryogenic Embedded System to Support Quantum Computing: From 5-nm FinFET to Full Processor
2023
·
Paul R. Genssler
, Florian Klemme
, et al.
·
IEEE Transactions on Quantum Engineering
·
22
PDF
Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations
2020
·
Chetan Kumar Dabhi
, Shivendra Singh Parihar
, et al.
·
IEEE Transactions on Electron Devices
·
22
Efficient Implementation of Max-Pooling Algorithm Exploiting History-Effect in Ferroelectric-FinFETs
2022
·
Musaib Rafiq
, Shivendra Singh Parihar
, et al.
·
IEEE Transactions on Electron Devices
·
19
Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs
2023
·
Shivendra Singh Parihar
, Girish Pahwa
, et al.
·
IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
·
14
Design Automation for Cryogenic CMOS Circuits
2023
·
Victor M. van Santen
, Marcel Walter
, et al.
·
Proceedings - ACM IEEE Design Automation Conference
·
12
A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs
2023
·
Shivendra Singh Parihar
, Ahtisham Pampori
, et al.
·
IEEE Journal of the Electron Devices Society
·
10
PDF
Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs
2023
·
Shivendra Singh Parihar
, Simon Thomann
, et al.
·
IEEE Open Journal of Circuits and Systems
·
10
PDF
5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing
2023
·
Shivendra Singh Parihar
, Simon Thomann
, et al.
·
Conference digest
·
9
An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K
2025
·
Hafeez Raza
, Shivendra Singh Parihar
, et al.
·
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
·
8
Characterization and Modeling of 14-/16-nm FinFET-Based LDMOS
2023
·
Anirban Kar
, Shivendra Singh Parihar
, et al.
·
IEEE Transactions on Electron Devices
·
6
Characterization and Global Parameter Extraction of bulk MOSFETs using BSIM-BULK Model
2018
·
Shivendra S. Parihar
, Chandan Jha
, et al.
·
IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)
·
6
Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction
2024
·
Shivendra Singh Parihar
, Girish Pahwa
, et al.
·
IEEE International Reliability Physics Symposium proceedings
·
4
Self-Heating characterization and modeling of 5nm technology node FinFETs
2022
·
Shivendra S. Parihar
, Jun Z. Huang
, et al.
·
Conference digest
·
4
Analysis and Compact Modeling of Drain-Extended FinFET
2019
·
Vikash Kumar
, Chetan Kumar Dabhi
, et al.
·
4
Energy-efficient cryogenic ternary content addressable memory using ferroelectric SQUID
2025
·
Shamiul Alam
, Simon Thomann
, et al.
·
npj Unconventional Computing
·
3
PDF
Cryogenic Hyperdimensional In-Memory Computing Using Ferroelectric TCAM
2025
·
Shivendra Singh Parihar
, Shubham Kumar
, et al.
·
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
·
3
Unveiling the Hidden Impact of Self-Heating on Ferroelectric FinFET and FDSOI based In-Memory Computing
2024
·
Swetaki Chatterjee
, Nistha Baruah
, et al.
·
IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
·
3
Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs
2024
·
Anirban Kar
, Shivendra Singh Parihar
, et al.
·
IEEE Journal of the Electron Devices Society
·
3
PDF
High-Frequency Characterization and Modeling of Low and High Voltage FinFETs for RF SoCs
2023
·
Yogesh S. Chauhan
, Anirban Kar
, et al.
·
IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
·
3
Benchmarking Cryogenic Circuits using 5 nm FinFETs for Quantum Processing
2025
·
Anirban Kar
, Shivendra Singh Parihar
, et al.
·
IEEE International Symposium on Circuits and Systems proceedings
·
2
Cryo-CACTI: Cryogenic-Aware CACTI for Cache Modeling Down to 10K in Advanced 7nm FinFETs
2025
·
Divya Praneetha Ravipati
, Victor M. van Santen
, et al.
·
IEEE Transactions on Computers
·
2
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Works count:
46
Citation count:
402
H-index:
10
I10-index:
11
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