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E. Rijpkema

Observed names: EDWIN RIJPKEMA, Edwin Rijpkema
OpenAlex ID: A5032367138
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
2003 · E. Rijpkema, Kees Goossens, et al. · Design, Automation, and Test in Europe · 375
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification
2005 · K. Goossens, J. Dielissen, et al. · Design, Automation, and Test in Europe · 188
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip
2003 · E. Rijpkema, K.G.W. Goossens, et al. · Design, Automation, and Test in Europe · 181
Compaan
2000 · Bart Kienhuis, Edwin Rijpkema, et al. · International Symposium on Hardware/Software Codesign (CODES) · 168
Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip
2003 · E. Rijpkema, K. Goossens, et al. · IEE Proceedings - Computers and Digital Techniques · 136
Guaranteeing the Quality of Services in Networks on Chip
2003 · Kees Goossens, John Dielissen, et al. · Springer eBooks · 91
Cost-performance trade-offs in networks on chip: a simulation-based approach
2004 · S.G. Pestana, E. Rijpkema, et al. · 89
A Router Architecture for Networks on Silicon
2001 · E. Rijpkema, Kees Goossens, et al. · 68
An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration
2004 · A. Rădulescu, J. Dielissen, et al. · 63
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration
2004 · A. Radulescu, J. Dielissen, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 60
Cost-performance trade-offs in networks on chip: a simulation-based approach
2004 · S.G. Pestana, E. Rijpkema, et al. · Design, Automation, and Test in Europe · 50
Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Aethereal Network on Chip
2005 · Om Prakash Gangwal, Andrei Rădulescu, et al. · Philips Research · 46
Compaan: deriving process networks from Matlab for embedded signal processing architectures
2002 · B. Kienhuis, E. Rijpkema, et al. · International Symposium on Hardware/Software Codesign (CODES) · 43
An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration
2004 · A. Radulescu, J. Dielissen, et al. · Design, Automation, and Test in Europe · 41
Deadlock Prevention in the Æthereal Protocol
2005 · Biniam Gebremichael, Frits Vaandrager, et al. · Lecture notes in computer science · 32
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A strategy for determining a Jacobi specific dataflow processor
2002 · E. Rijpkema, G. Hekstra, et al. · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · 18
Deriving Process Networks From Nested Loop Algorithms
2000 · EDWIN RIJPKEMA, ED F. DEPRETTERE, et al. · Parallel Processing Letters · 11
Translating Imperative Affine Nested Loop Programs into Process Networks
2002 · Ed F. Deprettere, Edwin Rijpkema, et al. · Lecture notes in computer science · 8
Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
2008 · E. Rijpkema, K. G. W. Goossens, et al. · Design, Automation, and Test in Europe · 7
High level modeling for parallel executions of nested loop algorithms
2002 · E.F. Deprettere, E. Rijpkema, et al. · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · 5
Service-Based Design of Systems on Chip and Networks on Chip
2005 · Kees Goossens, Santiago González Pestana, et al. · Philips Research · 4
Application and architecture modeling for parallel execution of Jacobi-type algorithms
2003 · E.F. Deprettere, E. Rijpkema, et al. · Asilomar Conference on Signals, Systems and Computers (ACSSC)
Works count: 32
Citation count: 1,684
H-index: 16
I10-index: 17
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