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Jitendra Kumar Saini
Institutions:
Vignan's Foundation for Science, Technology & Research,
JECRC University,
Manipal University Jaipur
Observed institutions:
Birla Institute of Technology, Mesra,
Vignan's Foundation for Science, Technology & Research,
JECRC University,
Manipal University Jaipur
ORCID:
0000-0003-4714-3984
Observed ORCID:
0000-0003-4714-3984
OpenAlex ID:
A5032513904
Fast and energy efficient full adder circuit using 14 CNFETs
2020
·
Jitendra Kumar Saini
, Avireni Srinivasulu
, et al.
·
Solid State Electronics Letters
·
13
PDF
A Low Power - High Speed CNTFETs Based Full Adder Cell With Overflow Detection
2019
·
Jitendra Kumar Saini
, Avireni Srinivasulu
, et al.
·
Micro and Nanosystems
·
13
Low Power - High Speed Magnitude Comparator Circuit Using 12 CNFETs
2018
·
Jitendra Kumar Saini
, Avireni Srinivasulu
, et al.
·
International SoC Design Conference
·
9
High-Performance Low-Power 5:2 Compressor With 30 CNTFETs Using 32 nm Technology
2019
·
Jitendra Kumar Saini
, Avireni Srinivasulu
, et al.
·
International Journal of Sensors Wireless Communications and Control
·
6
A Novel Simple Differentiator Circuit Based on Carbon Nano Tube Field Effect Transistors Voltage Difference Transconductance Amplifier
2019
·
Avireni Bhargav
, Jitendra Kumar Saini
·
Micro and Nanosystems
·
5
A Low-Voltage Distinctive Source-Based Sense Amplifier for Memory Circuits Using FinFETs
2018
·
Arti Ahir
, Jitendra Kumar Saini
, et al.
·
Advances in intelligent systems and computing
·
4
A Full Adder Design with CNFETs for Real Time, Fault Tolerant and Mission Critical Applications
2020
·
Avireni Srinivasulu
, Jitendra Kumar Saini
, et al.
·
Electronics ETF
·
1
PDF
Simulation of Optical ISL with 48 Transponders and Performance Analysis Using Ber and Q-Factor
2019
·
Avireni Bhargav
, Jitendra Kumar Saini
·
Journal of Optical Communications
·
1
Utilization of CNFET Technology for Low-Power High-Speed 12 Transistor Full Adder Circuit
2019
·
Priyansh Jain
, Jitendra Kumar Saini
·
Journal of Advanced Research in Dynamical and Control Systems
Real-time Error Detectable Multiplier Circuit Using CNFET Technology
2019
·
Jitendra Kumar Saini
, Avireni Srinivasulu
, et al.
·
Journal of Advanced Research in Dynamical and Control Systems
Analyzation of Q-factor and BER of OISL with 36 Transponders
2018
·
Avireni Bhargav
, Jitendra Kumar Saini
Design and Development of Low Voltage Distribution Board for CBM-MUCH Experiment
2013
·
Vikas Jain
, Susanta Kumar Pal
, et al.
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Works count:
12
Citation count:
52
H-index:
5
I10-index:
2
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