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Madhav P. Desai

Observed names: DESAI, MP, Desai, Madhav, Desai, Madhav P., M. Desai, M.P Desai, M.P. Desai, Madhav Desai, Madhav P Desai
OpenAlex ID: A5033005768
On the connectivity in finite ad hoc networks
2002 · M. Desai, D. Manjunath · IEEE Communications Letters · 190
A characterization of the smallest eigenvalue of a graph
1994 · Madhav Desai, Vasant Rao · Journal of Graph Theory · 139
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The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance
2002 · N.R. Mohapatra, M.P. Desai, et al. · IEEE Transactions on Electron Devices · 92
Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors
2003 · N.R. Mohapatra, M.P. Desai, et al. · IEEE Transactions on Electron Devices · 78
Sizing of clock distribution networks for high performance CPU chips
1996 · Madhav P. Desai, Radenko Cvijetic, et al. · ACM/IEEE Design Automation Conference (DAC) · 68
The Effect of LAC Doping on Deep Submicrometer Transistor Capacitances and its Influence on Device RF Performance
2004 · K. Narasimhulu, M.P. Desai, et al. · IEEE Transactions on Electron Devices · 36
A Low-Latency, Low-Power FPGA Implementation of ECG Signal Characterization Using Hermite Polynomials
2021 · Madhav P. Desai, Gabriel Caffarena, et al. · Electronics · 27
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Variance reduction in Monte Carlo capacitance extraction
2005 · S.H. Batterywala, M.P. Desai · International Conference on VLSI Design · 24
On the convergence of block relaxation methods for circuit simulation
1989 · M.P. Desai, I.N. Hajj · IEEE Transactions on Circuits and Systems · 22
A state assignment scheme targeting performance and area
1999 · B.N.V.M. Gupta, H. Narayanan, et al. · International Conference on VLSI Design · 19
On the Convergence of Reversible Markov Chains
1993 · Madhav P. Desai, Vasant B. Rao · SIAM Journal on Matrix Analysis and Applications · 18
Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches
2002 · Maryam Shojaei Baghini, Madhav P. Desai · Asia and South Pacific Design Automation Conference (ASP-DAC) · 15
Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics
2003 · N.R. Mohapatra, M.P. Desai, et al. · International Conference on VLSI Design · 14
Decomposition of finite state machines for area, delay minimization
2003 · R.S. Shelar, M.P. Desai, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 14
Reconfigurable finite-state machine based IP lookup engine for high-speed router
2003 · M. Desai, R. Gupta, et al. · IEEE Journal on Selected Areas in Communications · 13
Orthogonal partitioning and gated clock architecture for low power realization of FSMs
2002 · R.S. Shelar, H. Narayanan, et al. · Annual IEEE International ASIC Conference and Exhibit · 13
The Click2NetFPGA toolchain
2012 · Teemu Rinta-aho, Mika Karlstedt, et al. · 12
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
2007 · Sameer Sahasrabuddhe, Hakim Raja, et al. · International Conference on VLSI Design · 11
Interconnect delay minimization using a novel pre-mid-post buffer strategy
2003 · V. Prasad, M.P. Desai · International Conference on VLSI Design · 11
The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function
2003 · M.P Desai, H Narayanan, et al. · Discrete Applied Mathematics · 11
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Some results characterizing the finite time behaviour of the simulated annealing algorithm
1999 · Madhav P Desai · Sadhana · 11
A systematic technique for verifying critical path delays in a 300MHz Alpha CPU design using circuit simulation
1996 · Madhav P. Desai · ACM/IEEE Design Automation Conference (DAC) · 11
Fast DC analysis and its application to combinatorial optimization problems
2006 · G. Trivedi, M.P. Desai, et al. · International Conference on VLSI Design · 10
Robust Elmore delay models suitable for full chip timing verification of a 600MHz CMOS microprocessor
1998 · Nevine Nassif, Madhav P. Desai, et al. · ACM/IEEE Design Automation Conference (DAC) · 9
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A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients
2015 · Nanditha P. Rao, Madhav P. Desai · Euromicro Conference on Digital System Design (DSD) · 8
Works count: 77
Citation count: 977
H-index: 14
I10-index: 23
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