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D. Tilak Raju
Observed names:
D Tilak Raju,
Tilak Raju Daram
Institution:
Vignan's Foundation for Science, Technology & Research
Observed institution:
Vignan's Foundation for Science, Technology & Research
ORCID:
0000-0002-4360-6067
Observed ORCID:
0000-0002-4360-6067
OpenAlex ID:
A5033330098
Design and Implementation of 3*3 Array Multiplier using DPTL Logic
2020
·
D. Tilak Raju
, M. D. S. Manasa
·
International Journal of Engineering Research and
·
6
PDF
Investigation of Error-Tolerant Approximate Multipliers for Image Processing Applications
2022
·
D. Tilak Raju
, Y. Srinivasa Rao
·
Lecture notes in networks and systems
·
3
Design and FPGA Synthesis of a Majority Logic Approximate Multiplier
2026
·
D Tilak Raju
, Ettamsetti Naga Nandini Devi
, et al.
·
International Conference on Advanced Computing and Knowledge Engineering (ICACKE)
Design and Implementation of Mux-based Approximate Modified Wallace Tree Multiplier for Image Processing Applications
2026
·
D Tilak Raju
, Konathala Mounika Ganga Nagamani
, et al.
·
International Conference on Trends in Electronics and Informatics (ICOEI)
Multiuser Detection for NOMA-PD-SCMA System in Nakagami-m Fading Channel Using DNN Algorithm
2026
·
G. Nooka Raju
, M. S. Hussain
, et al.
·
Lecture notes in networks and systems
Efficient Design of Static Segment Inaccurate Multiplier using Leading One-Bit Approach for Image Processing Applications
2022
·
Tilak Raju Daram
, Y. Srinivasa Rao
·
Research Square
PDF
Efficient Design of Rounding Based Static Segment Imprecise Multipliers for Error Tolerance Application
2022
·
D. Tilak Raju
, Y. Srinivasa Rao
·
Journal of Electronic Testing
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Works count:
7
Citation count:
9
H-index:
2
I10-index:
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