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Anindya Sundar Dhar

Observed names: A S Dhar, A. S. Dhar, A. Sundar Dhar, A.S. Dhar, Anindya S Dhar, Anindya S. Dhar, Anindya.S. Dhar, Dhar, Anindya S., Dhar, Anindya Sundar
ORCID: 0000-0001-5288-4715
Observed ORCID: 0000-0001-5288-4715
OpenAlex ID: A5034075191
CORDIC Architectures: A Survey
2010 · B. Lakshmi, A. S. Dhar · VLSI design · 84
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A VLSI array architecture for realization of DFT, DHT, DCT and DST
2001 · K. Maharatna, A.S. Dhar, et al. · Signal Processing · 58
FPGA realization of a CORDIC based FFT processor for biomedical signal processing
2001 · Ayan Banerjee, Anindya Sundar Dhar, et al. · Microprocessors and Microsystems · 58
An array architecture for fast computation of discrete Hartley transform
1991 · A.S. Dhar, S. Banerjee · IEEE Transactions on Circuits and Systems · 55
CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis
2006 · K.C. Ray, A.S. Dhar · IEE Proceedings - Circuits Devices and Systems · 33
Real-time fault-tolerance with hot-standby topology for conditional sum adder
2015 · Atin Mukherjee, Anindya Sundar Dhar · Microelectronics Reliability · 32
Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities
2017 · Subrahmanyam Mula, Vinay Chakravarthi Gogineni, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 25
Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification
2018 · Subrahmanyam Mula, Vinay Chakravarthi Gogineni, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 24
VLSI architecture for low latency radix-4 CORDIC
2011 · B. Lakshmi, A.S. Dhar · Computers & Electrical Engineering · 23
A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC
2005 · M. Chakraborty, A.S. Dhar, et al. · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 23
Architectural design and FPGA implementation of radix-4 CORDIC processor
2010 · Kaushik Bhattacharyya, Rakesh Biswas, et al. · Microprocessors and Microsystems · 20
A Novel $k$-times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom
2022 · Rajen Kumar Patra, Anindya Sundar Dhar · IEEE Signal Processing Letters · 19
VLSI architecture for parallel radix-4 CORDIC
2012 · B. Lakshmi, A.S. Dhar · Microprocessors and Microsystems · 19
A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders
2018 · Avishek Sinha Roy, Anindya Sundar Dhar · IEEE International Symposium on Circuits and Systems proceedings · 18
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Low-Delay Parallel Architecture for Fractal Image Compression
2015 · Mamata Panigrahy, Indrajit Chakrabarti, et al. · Circuits Systems and Signal Processing · 17
FPGA implementation of discrete fractional Fourier transform
2010 · M. V. N. V. Prasad, K. C. Ray, et al. · International Conference on Signal Processing and Communications (SPCOM) · 16
A Novel Nested Array for Real-Valued Sources Exploiting Array Motion
2021 · Rajen Kumar Patra, Anindya Sundar Dhar · IEEE Signal Processing Letters · 15
On Fast and Exact Computation of Error Metrics in Approximate LSB Adders
2020 · Avishek Sinha Roy, Rajdeep Biswas, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 15
Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations
2017 · Ayan Palchaudhuri, Anindya Sundar Dhar · Journal of Electronic Testing · 14
Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs
2016 · Ayan Palchaudhuri, Anindya Sundar Dhar · International Conference on VLSI Design · 14
Sampled analog architecture for DCT and DST
2004 · A.K. Mal, A. Basu, et al. · IEEE International Symposium on Circuits and Systems proceedings · 14
Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies
2019 · Ayan Palchaudhuri, Anindya Sundar Dhar · Journal of Parallel and Distributed Computing · 13
Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer
2012 · Ayan Banerjee, Anindya Sundar Dhar · Journal of Signal Processing Systems · 13
SIBAM—Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications
2020 · Avishek Sinha Roy, Anindya Sundar Dhar · IEEE Transactions on Circuits & Systems II Express Briefs · 12
Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise
2019 · Subrahmanyam Mula, Vinay Chakravarthi Gogineni, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 12
Works count: 145
Citation count: 1,053
H-index: 16
I10-index: 33
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