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Satyajit Bora
Institution:
Indian Institute of Technology Guwahati
Observed institutions:
Tezpur University,
Indian Institute of Technology Guwahati
ORCID:
0000-0002-9611-113X
Observed ORCID:
0000-0002-9611-113X
OpenAlex ID:
A5035560109
A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications
2020
·
Satyajit Bora
, Roy Paily
·
IEEE Transactions on Circuits & Systems II Express Briefs
·
45
An Efficient Architecture for QRS Detection in FPGA Using Integer Haar Wavelet Transform
2020
·
Soham Talukder
, Rajan Singh
, et al.
·
Circuits Systems and Signal Processing
·
31
Design and Implementation of Blind Assistance System Using Real Time Stereo Vision Algorithms
2016
·
Vaddi Chandra Sekhar
, Satyajit Bora
, et al.
·
International Conference on VLSI Design
·
20
Design and Implementation of Adaptive Binary Divider for Fixed-Point and Floating-Point Numbers
2021
·
Satyajit Bora
, Roy Paily
·
Circuits Systems and Signal Processing
·
7
Impact of Pipelining on Low Power IoT applicable RISC-V ISA Core Micro-architectures
2024
·
Titu Mary Ignatius
, Satyajit Bora
, et al.
·
IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
·
5
Design and Implementation of 2-Input OR Gate based on XGM properties of Semiconductor Optical Amplifier
2014
·
Chandra Kamal Borgohain
, Chakresh Kumar
, et al.
·
International Journal of Advances in Telecommunications Electrotechnics Signals and Systems
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Works count:
6
Citation count:
108
H-index:
5
I10-index:
3
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