Author

D. Muralidharan

Observed names: Muralidharan D, Muralidharan Dakshinamoorthy

Institution: SASTRA University

Observed institution: SASTRA University

ORCID: 0000-0001-7378-6866

Observed ORCID: 0000-0001-7378-6866

OpenAlex ID: A5035631493

Predicting Tumor Sensitivity to Chemotherapeutic Drugs in Oral Squamous Cell Carcinoma Patients

2018 · Beaulah Mary Robert, Muralidharan Dakshinamoorthy, et al. · Scientific Reports · 33

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Credit Card Fraud Data Analysis and Prediction Using Machine Learning Algorithms

2025 · Karunya R.V., Samyuktha Ganesh, et al. · Security and Privacy · 10

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Cryptography‐based deep artificial structure for secure communication using IoT‐enabled cyber‐physical system

2021 · Chakrapani Kannan, Muralidharan Dakshinamoorthy, et al. · IET Communications · 9

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Security in sequence: NIST-adherent design of a hybrid random number generator with SRAM-based PUF

2025 · R. Sivaraman, Srinidhi Magesh, et al. · Analog Integrated Circuits and Signal Processing · 6

Fixed point multi-bit approximate adder based convolutional neural network accelerator for digit classification inference

2020 · Manikandan Nagarajan, A. Sasikumar, et al. · Journal of Intelligent & Fuzzy Systems · 6

Double Compression of Test Data Using Huffman Code

2012 · R. Aarthi, D. Muralidharan, et al. · 5

A low power vernier Time-To-Digital converter using adiabatic logic

2017 · R. Mahima, D. Muralidharan · International Conference on Networks & Advances in Computational Technologies (NetACT) · 3

Optimal Hamming Distance Model for Crypto Cores against Side Channel Threats

2014 · K. P. Sridhar, D. Muralidharan · 3

A HDL based reduced area NOC router architecture

2013 · M. S. Suraj, D. Muralidharan, et al. · International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT) · 3

Missing Values Treatment and Feature Reduction Analysis to Enhance Classification

2020 · D. Muralidharan, K. Renuka, et al. · Journal of Computer Science · 2

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Automation of wireless Telecom Node Commands of Network Management System

2016 · N. Balameena, D. Muralidharan · Indian Journal of Science and Technology · 2

Towards robust true random number generation: addressing vulnerabilities in dual entropy source design

2025 · R. Sivaraman, H. Naresh Kumar, et al. · Analog Integrated Circuits and Signal Processing · 1

FPGA Governed Edge Device Confidentiality: Lightweight Cryptography with Enhanced Security

2024 · Sivaraman R, Gowtham S, et al. · Control Instrumentation System Conference (CISCON) · 1

Performance And Security Enhanced Improved Hill Cipher

2023 · Muralidharan D, Brindha G R, et al. · International Conference on Electrical, Computer and Communication Technologies (ICECCT) · 1

Region-Aware Trace Signal Selection Using Machine Learning Technique for Silicon Validation and Debug

2019 · R. Agalya, R. Muthaiah, et al. · Computer Modeling in Engineering & Sciences · 1

High Throughput Pipelining NoC using Clumsy Flow Control

2016 · S. Anu Karpaga, D. Muralidharan · Indian Journal of Science and Technology · 1

Bus Based Synchronization Method for CHIPPER Based NoC

2016 · D. Muralidharan, R. Muthaiah · Scientific Programming · 1

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SiameseHTD: Golden-Chip-Free Hardware Trojan Detection Using Power Traces

2026 · Neha K, Varshini Y S, et al.

A Fully Combinational GF(2 16 ) Multiplier for Using Hierarchical Karatsuba–Ofman and Matrix-Based Modular Reduction Technique for Crypto-Primitive Generation

2026 · Chandrasekhar Srikanth D, Muralidharan D, et al. · IEEE International Conference on Recent Advances in Electronics, Communication, Computing, Automation and Power (RECCAP)

Design and Investigation of Prime Length Non-Identical Entropy Source for True Random Sequence Generation Using CMOS 180nm Technology

2024 · Sivaraman R, Santhosh R, et al. · International Conference on Innovations in Communications, Electrical and Computer Engineering (ICICEC)

Pipelined chipper based noc for performance enhancement

2017 · U. Sivaranjani, D. Muralidharan, et al. · International Conference on Networks & Advances in Computational Technologies (NetACT)

Hybrid Integration in 3D NoC with Efficient Path Establishment Mechanism in Circuit Switching

2016 · S. Aishwarya, D. Muralidharan · Indian Journal of Science and Technology

A Novel Approach for X-filling and Reordering Test Vectors for Power Reduction

2012 · C. R. Supreta Devi, Kartik Venkatraman, et al. · Research Journal of Applied Sciences Engineering and Technology

An Innovative Test Data Compression Method Using Scan Chain Compaction

2012 · S s Sowmiyaa, D. Muralidharan

Design and Implementation of a Fractional Bit Encoded Spatial Modulator for the Versatile Multiple-Input Multiple Output (MIMO) System

2010 · Dhirendra Kumar Tripathi, D. Muralidharan, et al. · CiiT international journal of programmable device circuits and systems

Works count: 25

Citation count: 87

H-index: 5

I10-index: 1