Get started
Author

Shaojun Wei

Observed names: ShaoJun WEI, ShaoJun Wei, Shaojun WEI, Wei Shaojun, Wei, Shaojun
Observed institutions: University of Mons, Intel (United States), Institute of Microelectronics, Beijing National Research Center for Information Science and Technology, Beihang University, Tsinghua University
ORCID: 0000-0001-5117-7920
Observed ORCID: 0000-0001-5117-7920
OpenAlex ID: A5036023084
Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns
2017 · Fengbin Tu, Shouyi Yin, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 324
FP-BNN: Binarized neural network on FPGA
2017 · Shuang Liang, Shouyi Yin, et al. · Neurocomputing · 308
A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications
2019 · Leibo Liu, Jianfeng Zhu, et al. · ACM Computing Surveys · 283
PDF
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications
2017 · Shouyi Yin, Peng Ouyang, et al. · IEEE Journal of Solid-State Circuits · 213
Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT
2020 · Neng Zhang, Bohan Yang, et al. · IACR Transactions on Cryptographic Hardware and Embedded Systems · 193
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration
2022 · Fengbin Tu, Yiqi Wang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 155
FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction
2023 · Yubin Qin, Yang Wang, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 132
PDF
TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes
2022 · Fengbin Tu, Zihan Wu, et al. · IEEE Journal of Solid-State Circuits · 102
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS
2019 · Ruiqi Guo, Yonggang Liu, et al. · Symposium on VLSI Circuits · 101
ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration
2022 · Fengbin Tu, Yiqi Wang, et al. · IEEE Journal of Solid-State Circuits · 97
A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications
2017 · Shouyi Yin, Peng Ouyang, et al. · Symposium on VLSI Circuits · 94
A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing
2022 · Yang Wang, Yubin Qin, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 93
A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium
2021 · Cankun Zhao, Neng Zhang, et al. · IACR Transactions on Cryptographic Hardware and Embedded Systems · 91
PDF
A Multilevel Cell STT-MRAM-Based Computing In-Memory Accelerator for Binary Convolutional Neural Network
2018 · Yu Pan, Peng Ouyang, et al. · IEEE Transactions on Magnetics · 89
RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM
2018 · Fengbin Tu, Weiwei Wu, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 79
CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme
2021 · Xiangren Chen, Bohan Yang, et al. · IACR Transactions on Cryptographic Hardware and Embedded Systems · 77
PDF
A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS
2018 · Shouyi Yin, Peng Ouyang, et al. · Symposium on VLSI Circuits · 74
Polyhedral model based mapping optimization of loop nests for CGRAs
2013 · Dajiang Liu, Shouyi Yin, et al. · ACM/IEEE Design Automation Conference (DAC) · 73
A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes
2022 · Fengbin Tu, Zihan Wu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 69
Efficient Hardware Architecture of Softmax Layer in Deep Neural Network
2018 · Ruofei Hu, Binren Tian, et al. · IEEE International Conference on Digital Signal Processing (DSP) · 68
LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR
2021 · Yihong Zhu, Min Zhu, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 67
9.2 A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction
2021 · Huiyu Mo, Wenping Zhu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 66
20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models
2024 · Ruiqi Guo, Lei Wang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 64
Wafer-Scale Computing: Advancements, Challenges, and Future Perspectives [Feature]
2024 · Yang Hu, Xinhan Lin, et al. · IEEE Circuits and Systems Magazine · 63
PDF
Energy- and Area-Efficient Recursive-Conjugate-Gradient-Based MMSE Detector for Massive MIMO Systems
2020 · Leibo Liu, Guiqiang Peng, et al. · IEEE Transactions on Signal Processing · 63
Works count: 606
Citation count: 8,131
H-index: 43
I10-index: 188
Year
Topic
Type