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Saburo Muroga

Observed names: Muroga, Saburo, Muroga, Saburo., S. Muroga
OpenAlex ID: A5036195592
Threshold logic and its applications
1971 · Saburo Muroga · CERN Document Server (European Organization for Nuclear Research) · 894
The transduction method-design of logic networks based on permissible functions
1989 · S. Muroga, Y. Kambayashi, et al. · IEEE Transactions on Computers · 234
Theory of majority decision elements
1961 · Saburo Muroga, Iwao Toda, et al. · Journal of the Franklin Institute · 166
Enumeration of Threshold Functions of Eight Variables
1970 · S. Muroga, T. Tsuboi, et al. · IEEE Transactions on Computers · 94
On the Capacity of a Discrete Channel. I Mathematical expression of capacity of a channel which is disturbed by noise in its every one symbol and expressible in one state diagram
1953 · Saburo Muroga · Journal of the Physical Society of Japan · 66
VLSI system design
1982 · Saburo Muroga · 63
Majority Decision Functions of up to Six Variables
1962 · S. Muroga, I. Toda, et al. · Mathematics of Computation · 54
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Timing optimization for multi-level combination networks
1990 · K.-C. Chen, S. Muroga · ACM/IEEE Design Automation Conference (DAC) · 43
Synthesis of Networks with a Minimum Number of Negative Gates
1971 · T. Ibaraki, S. Muroga · IEEE Transactions on Computers · 42
Lower Bounds of the Number of Threshold Functions and a Maximum Weight
1965 · Saburo Muroga · IEEE Transactions on Electronic Computers · 37
Adaptive Linear Classifier by Linear Programming
1970 · Toshihide Ibaraki, Saburo Muroga · IEEE Transactions on Systems Science and Cybernetics · 35
Design of Optimal Switching Networks by Integer Programming
1972 · Saburo Muroga, Toshihide Ibaraki · IEEE Transactions on Computers · 33
Absolute minimization of completely specified switching functions
1991 · S.J. Hong, S. Muroga · IEEE Transactions on Computers · 30
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SYLON-DREAM: a multi-level network synthesizer
2003 · K.-C. Chen, S. Muroga · International Conference on Computer Aided Design · 22
The Parametron Digital Computer MUSASINO-1
1959 · S. Muroga, K. Takashima · IEEE Transactions on Electronic Computers · 21
An implicit enumeration program for zero-one integer programming
1972 · T. Ibaraki, T. K. Liu, et al. · International Journal of Parallel Programming · 19
Lower Bound of the Number of Threshold Functions
1966 · S. Muroga, I. Toda · IEEE Transactions on Electronic Computers · 19
Useless prime implicants of incompletely specified multiple-output switching functions
1980 · Robert B. Cutler, Saburo Muroga · International Journal of Parallel Programming · 16
Optimal One-Bit Full Adders With Different Types of Gates
1974 · Tso-Kai Liu, K.R. Hohulin, et al. · IEEE Transactions on Computers · 16
Optimal Networks of NOR-OR Gates for Functions of Three Variables
1972 · Charles R. Baugh, C. S. Chandersekaran, et al. · IEEE Transactions on Computers · 16
Logical Design of Optimal Digital Networks by Integer Programming
1970 · Saburo Muroga · Springer eBooks · 14
Functional forms of majority functions and a necessary and sufficient condition for their realizability
1961 · Saburo Muroga · Annual Symposium on Switching Circuit Theory and Logical Design (SWCT) · 14
Design of MOS networks in single-rail input logic for incompletely specified functions
1988 · H.C. Lai, S. Muroga · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 13
Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables
1985 · Ming Huei Young, Saburo Muroga · IEEE Transactions on Computers · 13
Input assignment algorithm for decoded-PLAs with multi-input decoders
2003 · Kuang-Chien Chen, S. Muroga · International Conference on Computer Aided Design · 12
Works count: 134
Citation count: 2,170
H-index: 17
I10-index: 28
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