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P. Prinetto

Observed names: PRINETTO, Paolo Ernesto, Paolo PRINETTO, Paolo Prinetto, Paolo prinetto, Prinetto, P., Prinetto, Paolo, Prinetto, Paolo Ernesto
Observed institutions: IMT School for Advanced Studies Lucca, University of Udine, Universidade Federal do Rio Grande do Sul, Politecnico di Torino, Aix-Marseille Université, University of Tehran, Consorzio Interuniversitario Nazionale per l'Informatica, Université de Provence Aix-Marseille I, University of Turin
ORCID: 0000-0003-2400-8245
Observed ORCID: 0000-0003-2400-8245
OpenAlex ID: A5036258272
Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation
2004 · Benso, Alfredo, Prinetto, Paolo · Kluwer Academic Publishers eBooks · 179
Formal verification of hardware correctness: introduction and survey of current research
1988 · P. Camurati, P. Prinetto · Computer · 112
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits
1996 · F. Corno, P. Prinetto, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 107
A diagnostic test pattern generation algorithm
1990 · P. Camurati, D. Medina, et al. · Proceedings/Proceedings - International Test Conference · 102
An automatic test pattern generator for large sequential circuits based on Genetic Algorithms
1994 · P. Prinetto, M. Rebaudengo, et al. · Proceedings/Proceedings - International Test Conference · 95
A C/C++ source-to-source compiler for dependable applications
2002 · A. Benso, S. Chiusano, et al. · 86
A test pattern generation methodology for low power consumption
2002 · E. Corno, P. Prinetto, et al. · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 79
Testability analysis and ATPG on behavioral RT-level VHDL
1997 · F. Corno, P. Prinetto, et al. · Proceedings/Proceedings - International Test Conference · 72
A watchdog processor to detect data and control flow errors
2004 · A. Benso, S. Di Carlo, et al. · 59
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Diagnosis oriented test pattern generation
1990 · P. Camurati, A. Lioy, et al. · European Design Automation Conference · 57
Challenges and Solutions in Emerging Memory Testing
2017 · Elena Ioana Vatajelu, Paolo Prinetto, et al. · IEEE Transactions on Emerging Topics in Computing · 56
New static compaction techniques of test sequences for sequential circuits
1997 · F. Corno, P. Prinetto, et al. · 51
An on-line BIST RAM architecture with self-repair capabilities
2002 · A. Benso, S. Chiusano, et al. · IEEE Transactions on Reliability · 49
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STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability
2016 · Elena Ioana Vatajelu, Giorgio Di Natale, et al. · ACM Journal on Emerging Technologies in Computing Systems · 48
Industrial BIST of embedded RAMs
1995 · P. Camurati, P. Prinetto, et al. · IEEE Design & Test of Computers · 48
A software-based self test of CUDA Fermi GPUs
2013 · Stefano Di Carlo, Giulio Gambardella, et al. · Proceedings/Proceedings - European Test Workshop · 45
Software-Based Self-Test of Set-Associative Cache Memories
2010 · Stefano Di Carlo, Paolo Prinetto, et al. · IEEE Transactions on Computers · 45
March AB, march AB1: new march tests for unlinked dynamic memory faults
2006 · A. Benso, A. Bosio, et al. · 42
Control-flow checking via regular expressions
2002 · A. Benso, S. Di Carlo, et al. · Proceedings - Asian Test Symposium/Proceedings · 42
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Advanced techniques for GA-based sequential ATPGs
1996 · F. Corno, P. Prinetto, et al. · European Design and Test Conference · 41
Scan chain encryption for the test, diagnosis and debug of secure circuits
2017 · Mathieu Da Silva, Marie-lise Flottes, et al. · Proceedings/Proceedings - European Test Workshop · 37
Reliability in Application Specific Mesh-Based NoC Architectures
2008 · Fatemeh Refan, Homa Alemzadeh, et al. · IEEE International On-Line Testing Symposium (IOLTS) · 37
A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs
2014 · Stefano Di Carlo, Paolo Prinetto, et al. · IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) · 35
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Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment
2002 · A.M. Amendola, A. Benso, et al. · 35
HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs
2002 · A. Benso, S. Chiusano, et al. · Proceedings/Proceedings - International Test Conference · 34
Works count: 441
Citation count: 3,859
H-index: 29
I10-index: 111
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