Get started
Author

Chi-Lun Lo

Observed name: Chilun Lo
OpenAlex ID: A5036658435
A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS
2015 · Stacy Ho, Chi-Lun Lo, et al. · IEEE Journal of Solid-State Circuits · 66
A 4.5 mW CT Self-Coupled $\Delta\Sigma$ Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation
2015 · Chen-Yen Ho, Cong Liu, et al. · IEEE Journal of Solid-State Circuits · 63
A 64-fJ/Conv.-Step Continuous-Time $\Sigma \Delta$ Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital $\Delta \Sigma$ Truncator
2013 · Hung-Chieh Tsai, Chi-Lun Lo, et al. · IEEE Journal of Solid-State Circuits · 52
NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver, 23-dBm CMOS Power Amplifier, Power Management Unit, and Clock Management System for Low Cost Solution
2020 · Jongsoo Lee, Jaeyeol Han, et al. · IEEE Journal of Solid-State Circuits · 45
A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOS
2011 · Chia-Hsin Wu, Wen-Chieh Tsai, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 22
10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter
2021 · Chilun Lo, Jongmi Lee, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 19
A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOS
2014 · Stacy Ho, Chi-Lun Lo, et al. · Symposium on VLSI Circuits · 15
30.2 NB-IoT and GNSS All-in-One System-on-Chip Integrating RF Transceiver, 23dBm CMOS Power Amplifier, Power Management Unit and Clock Management System for Low-Cost Solution
2020 · Jongsoo Lee, Jaeyeol Han, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 13
15.2 A 4.5mW CT self-coupled ΔΣ modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation
2015 · Chen-Yen Ho, Cong Liu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 12
24.6 A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC
2025 · Cheng-En Hsieh, Gabriele Manganaro, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 8
A 1.04 - 4V, Digital-Intensive Dual-Mode BLE 5.0/IEEE 802.15.4 Transceiver SoC with extended range in 28nm CMOS
2019 · Nam-Seog Kim, Myoung-Gyun Kim, et al. · Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium · 7
A 75.1dB SNDR 840MS/s CT ΔΣ modulator with 30MHz bandwidth and 46.4fJ/conv FOM in 55nm CMOS
2013 · Chi-Lun Lo, Chen-Yen Ho, et al. · Symposium on VLSI Circuits · 6
A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS
2019 · Barosaim Sung, Chilun Lo, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 3
A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS
2017 · Jongmi Lee, Jongwoo Lee, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 2
A 1.2V 64fJ/conversion-step continuous-time ΣΔ modulator using asynchronous SAR quantizer and digital ΣΔ truncator
2012 · Hung-Chieh Tsai, Chi-Lun Lo, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 1
Works count: 15
Citation count: 334
H-index: 9
I10-index: 9
Year
Topic
Type