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Paresh Baidya
Observed names:
Baidya, Paresh,
P. Baidya
Institutions:
National Institute of Technology Jamshedpur,
Siksha O Anusandhan University,
Shiv Nadar University, Chennai
Observed institutions:
National Institute of Technology Jamshedpur,
Siksha O Anusandhan University,
Shiv Nadar University, Chennai
ORCID:
0009-0009-2647-4961
Observed ORCID:
0009-0009-2647-4961
OpenAlex ID:
A5036811610
IoT Based Secure Smart City Architecture Using Blockchain
2018
·
Rourab Paul
, Paresh Baidya
, et al.
·
International Conference on Data Science and Business Analytics (ICDSBA)
·
28
Mood-Based Movie Recommendation System
2022
·
Soumya S. Acharya
, Nandita Nupur
, et al.
·
Smart innovation, systems and technologies
·
4
Binary Field Point Multiplication Implementation in FPGA Hardware
2020
·
Suman Sau
, Paresh Baidya
, et al.
·
Smart innovation, systems and technologies
·
4
Secure multi-gigabit optical link design for high energy physics experiment with acceleration of more secure RC4 variant in reconfigurable platform
2020
·
R. Paul
, J. Mitra
, et al.
·
Journal of Instrumentation
·
4
PDF
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Hardware Accelerator on Reconfigurable Architecture
2024
·
Paresh Baidya
, Swagata Mandal
, et al.
·
IEEE Access
·
3
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture
2022
·
Baidya, Paresh
, Mondal, Swagata
, et al.
·
arXiv (Cornell University)
·
1
PDF
High-Speed Loop Unrolled Grain Architecture in Reconfigurable Hardware
2020
·
Paresh Baidya
, Rourab Paul
, et al.
·
Advances in intelligent systems and computing
·
1
A Lightweight Fault-Detection Scheme for Barrett Modular Multiplication Using Multiple Conditional Reduction Paths
2026
·
Paul, Rourab
, Baidya, Paresh
, et al.
·
arXiv (Cornell University)
PDF
Efficient Error Detection for NTT Using Algebraic Invariants (AIC) Checking for PQC and FHE on FPGA
2026
·
Rourab Paul
, Paresh Baidya
, et al.
·
ACM Transactions on Embedded Computing Systems
Error Detection Schemes for Barrett Modular Multiplication of CT-BU on FPGA in PQC and FHE
2026
·
Paresh Baidya
, Rourab Paul
, et al.
·
IEEE Transactions on Emerging Topics in Computing
Energy-Efficient NTT Sampler for Kyber Benchmarked on FPGA
2025
·
Baidya, Paresh
, Paul, Rourab
, et al.
·
arXiv (Cornell University)
PDF
Efficient Implementation of Knuth Yao Sampler on Reconfigurable Hardware
2024
·
Paresh Baidya
, Rourab Paul
, et al.
·
IEEE Computer Architecture Letters
Blockchain-Envisioned Post-Quantum Secure Sanitizable Signature for Audit Logs Management
2023
·
Srivastava, Vikas
, Baidya, Paresh
, et al.
·
arXiv (Cornell University)
PDF
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Works count:
15
Citation count:
45
H-index:
4
I10-index:
1
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