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Author

Jude Haris

Observed names: Haris, Jude, Haris, Jude Christudas
Observed institution: University of Glasgow
ORCID: 0000-0001-7359-3888
Observed ORCID: 0000-0001-7359-3888
OpenAlex ID: A5037278231
Designing Efficient LLM Accelerators for Edge Devices
2024 · Haris, Jude, Saha, Rappy, et al. · arXiv (Cornell University) · 31
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SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference
2021 · Jude Haris, Perry Gibson, et al. · International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) · 26
SECDA-TFLite: A toolkit for efficient development of FPGA-based DNN accelerators for edge inference
2022 · Jude Haris, Perry Gibson, et al. · Journal of Parallel and Distributed Computing · 15
AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators
2024 · Nicolas Bohm Agostini, Jude Haris, et al. · Proceedings of the CGO/Proceedings of the ... CGO · 6
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F-BFQ: Flexible Block Floating-Point Quantization Accelerator for LLMs
2025 · Haris, Jude, Cano, José · ENLIGHTEN (Jurnal Bimbingan dan Konseling Islam) · 2
Accelerating PoT Quantization on Edge Devices
2024 · Rappy Saha, Jude Haris, et al. · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 2
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Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA
2026 · Sharma, Vinamra, Fu, Xingjian, et al. · arXiv (Cornell University) · 1
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LLM-Driven Design Space Exploration of FPGA-based Accelerators
2026 · Sharma, Vinamra, Fu, Xingjian, et al. · arXiv (Cornell University) · 1
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Hardware Acceleration of Deep Neural Networks on Edge Devices with FPGAs
2020 · Jude Haris, José Cano · ENLIGHTEN (Jurnal Bimbingan dan Konseling Islam) · 1
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Automating FPGA Accelerator Design using Large Language Models
2026 · Sharma, Vinamra, Fu, Xingjian, et al. · ENLIGHTEN (Jurnal Bimbingan dan Konseling Islam)
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FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining
2026 · Saha, Rappy, Amirafshar, Nima, et al. · ENLIGHTEN (Jurnal Bimbingan dan Konseling Islam)
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FlexViT: A Flexible FPGA-Based Accelerator for Edge Vision Transformers
2026 · Hubert Dymarkowski, Xingjian Fu, et al. · International Conference on Field Programmable Logic and Applications (FPL)
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Automating FPGA Accelerator Design using Large Language Models
2026 · Sharma, Vinamra, Fu, Xingjian, et al. · ENLIGHTEN (Jurnal Bimbingan dan Konseling Islam)
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Hardware Profiling for SECDA on Edge Platforms
2026 · Haris, Jude, Saha, Rappy, et al. · ENLIGHTEN (Jurnal Bimbingan dan Konseling Islam)
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Defeat the Heap: Zero-Copy Data Movement in AXI4MLIR
2026 · Cohavi, Elam, Agostini, Nicolas Bohm, et al. · arXiv (Cornell University)
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Multi-Partner Project: dAIEDGE - A Network of Excellence for Distributed, Trustworthy, Efficient and Scalable AI at the Edge
2026 · Alain Pagani, José Cano, et al. · Design, Automation, and Test in Europe
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PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs
2026 · Rappy Saha, Jude Haris, et al. · IEEE transactions on circuits and systems for artificial intelligence.
Accelerating Transposed Convolutions on FPGA-Based Edge Devices
2025 · Jude Haris, José Cano · International Conference on Field Programmable Logic and Applications (FPL)
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Works count: 23
Citation count: 86
H-index: 4
I10-index: 3
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