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Chunseok Jeong

Observed names: C.-Y. Jeong, Chun-Seok Jeong
ORCID: 0009-0004-1666-7878
Observed ORCID: 0009-0004-1666-7878
OpenAlex ID: A5039665161
Newton: A DRAM-maker’s Accelerator-in-Memory (AiM) Architecture for Machine Learning
2020 · Mingxuan He, Choungki Song, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 228
A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications
2022 · Seongju Lee, Kyuyoung Kim, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 160
System Architecture and Software Stack for GDDR6-AiM
2022 · Yongkee Kwon, Kornijcuk Vladimir, et al. · IEEE Hot Chips Symposium · 88
IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System
2024 · Minseok Seo, Xuan Truong Nguyen, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 76
A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control
2018 · Jin Hee Cho, Jihwan Kim, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 62
High bandwidth memory(HBM) with TSV technique
2016 · Jong Chern Lee, Jihwan Kim, et al. · International SoC Design Conference · 62
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application
2022 · Daehan Kwon, Seongju Lee, et al. · IEEE Journal of Solid-State Circuits · 52
13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization
2024 · Jinhyung Lee, Kyungjun Cho, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 46
5-GHz Low-Phase Noise CMOS Quadrature VCO
2006 · C.-Y. Jeong, C. Yoo · IEEE Microwave and Wireless Components Letters · 44
18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface
2016 · Jong Chern Lee, Jihwan Kim, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 42
22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST
2020 · Dong Uk Lee, Ho Sung Cho, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 35
Memory-Centric Computing with SK Hynix's Domain-Specific Memory
2023 · Yongkee Kwon, Guhyun Kim, et al. · IEEE Hot Chips Symposium · 31
A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology
2009 · Young-Suk Seo, Jang-Woo Lee, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 26
Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM
2004 · Chunseok Jeong, Changsik Yoo, et al. · European Solid-State Circuits Conference (ESSCIRC) · 16
Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface
2012 · Jang-Woo Lee, Hong-Jung Kim, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 10
Analog Circuit Design Automation via Sequential RL Agents and Gm/ID Methodology
2024 · Sungweon Hong, Yunseob Tae, et al. · IEEE Access · 9
1.2V, 10MHz, low-pass Gm-C filter with Gm-cells based on triode-biased MOS and passive resistor in 0.13μm CMOS technology
2006 · Jun-Gi Jo, Changsik Yoo, et al. · Custom Integrated Circuits Conference · 9
23.4 A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller
2019 · Seongju Lee, Byungdeuk Jeon, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 8
Holistic approaches to memory solutions for the Autonomous Driving Era
2022 · Daeyong Shim, Chunseok Jeong, et al. · IEEE International Symposium on Circuits and Systems proceedings · 4
A Phase-Locked Loop with Embedded Analog-to-Digital Converter for Digital Control
2007 · Sooho Cha, Chunseok Jeong, et al. · ETRI Journal · 2
Digital delay locked loop with open-loop full-digital duty cycle corrector for high-speed DRAM interface
2004 · Chunseok Jeong, Changsik Yoo · 대한전자공학회 ISOCC
삼각형 망 모형의 법선 추정을 위한 개선된 Normal Voting 방법에 관한 연구 = Improvement of normal voting method for normal estimation of triangle mesh
2003 · 정춘석, Chunseok Jeong
Works count: 22
Citation count: 1,010
H-index: 14
I10-index: 15
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