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K. S. Sainarayanan

Observed names: K S Sainarayanan, K.S. Sainarayanan, KS Sainarayanan
OpenAlex ID: A5040967193
A Novel, Coupling Driven, Low Power Bus Coding Technique for Minimizing Capacitive Crosstalk in VLSI Interconnects
2006 · K.S. Sainarayanan, J.V.R. Ravindra, et al. · IEEE International Symposium on Circuits and Systems proceedings · 14
Minimizing simultaneous switching noise (SSN) using modified odd/even bus invert method
2006 · K.S. Sainarayanan, J.V.R. Ravindra, et al. · IEEE International Workshop on Electronic Design, Test and Applications (DELTA) · 10
Modified Area Efficient Temporal Coding Technique for Delay Minimization in VLSI interconnects
2006 · K. S. Sainarayanan, C Raghunandan, et al. · 대한전자공학회 ISOCC · 8
EDGE: Encoding and Decoding of Generic Data for Minimizing Switched Capacitance and Transition Density for Low Power VLSI Applications
2005 · J. V. R. Ravindra, K. S. Sainarayanan, et al. · 대한전자공학회 ISOCC · 8
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects
2007 · Chittarsu Raghunandan, K. S. Sainarayanan, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 7
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme
2007 · K S Sainarayanan, C Raghunandan, et al. · IEEE Computer Society Annual Symposium on VLSI · 7
Coding for Minimizing Energy in VLSI Interconnects
2006 · K. S. Sainarayanan, J. V. R. Ravindra, et al. · 7
Coupling aware energy-efficient data scrambling on memory-processor interfaces
2007 · K. S. Sainarayanan, J. V. R. Ravindra, et al. · IEEE International Conference on Industrial and Information Systems (ICIIS) · 6
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects
2008 · Chittarsu Raghunandan, K.S. Sainarayanan, et al. · International Symposium on Quality Electronic Design (ISQED) · 4
An Efficient Power Reduction Technique for Low Power Data I/O For Military Applications
2006 · J.V.R. Ravindra, K.S. Sainarayanan, et al. · IEEE/AIAA Digital Avionics Systems Conference (DASC) · 4
Bus encoding schemes for minimizing delay in VLSI interconnects
2007 · K. S. Sainarayanan, Chittarsu Raghunandan, et al. · Symposium on Integrated Circuits and Systems Design · 3
Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN)
2007 · C Raghunandan, K S Sainarayanan, et al. · IEEE International Symposium on Circuits and Systems proceedings · 3
Encoding with Repeater Insertion for Minimizing Delay in VLSI Interconnects
2006 · C Raghunandan, KS Sainarayanan, et al. · International Workshop on System-on-Chip for Real-Time Applications · 2
Bus coding to minimize redundant bit transitions
2007 · K S Sainarayanan, C Raghunandan, et al. · IEEE Region 10 Conference (TENCON) · 1
A novel deep submicron low power bus coding technique.
2005 · K. S. Sainarayanan, J. V. R. Ravindra, et al. · Circuits, Signals, and Systems · 1
Impact of process variations on bus-encoding schemes for delay minimization in VLSI interconnects
2007 · C. Raghunandan, K. S. Sainarayanan, et al. · IEEE Workshop on Signal Propagation on Interconnects (SPI)
Efficient Spatial-Temporal Coding Scheme for Minimizing Delay in Interconnects
2006 · K S Sainarayanan, C Raghunandan, et al. · IEEE Region 10 Conference (TENCON)
Works count: 17
Citation count: 85
H-index: 7
I10-index: 2
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