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Author

Atsushi Motozawa

Observed institution: Renesas Electronics (Japan)
ORCID: 0000-0002-4564-6249
Observed ORCID: 0000-0002-4564-6249
OpenAlex ID: A5041288806
An Attachable Fractional Divider Transforming an Integer-N PLL Into a Fractional-N PLL Achieving Only 0.35-psrms-Integrated-Jitter Degradation With SSC Capability
2023 · Atsushi Motozawa, Yasuyuki Hiraku, et al. · IEEE Solid-State Circuits Letters · 7
Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider
2023 · Atsushi Motozawa, Yasuyuki Hiraku, et al. · Electronics · 1
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An Attachable Fractional Divider Transforming an Integer-N PLL Into a Fractional-N PLL with SSC Capability
2022 · Atsushi Motozawa, Yasuyuki Hiraku, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 1
Modeling Technologies from Analog/Mixed-Signal Circuit Designer Viewpoint
2022 · Haruo Kobayashi, Hitoshi Aoki, et al. · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · 1
Works count: 4
Citation count: 10
H-index: 1
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