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Walker J. Turner

Observed names: Turner, Walker Joseph; Poulton, John; Song, Sanquan, W. J. Turner, Walker Turner
ORCID: 0000-0001-9230-7605
Observed ORCID: 0000-0001-9230-7605
OpenAlex ID: A5041378837
ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks
2020 · Haoxing Ren, George F. Kokai, et al. · ACM/IEEE Design Automation Conference (DAC) · 119
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
2018 · John W. Poulton, John M. Wilson, et al. · IEEE Journal of Solid-State Circuits · 74
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS
2023 · Yoshinori Nishi, John W. Poulton, et al. · IEEE Journal of Solid-State Circuits · 70
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization
2021 · Mingjie Liu, Walker J. Turner, et al. · Design, Automation, and Test in Europe · 52
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator
2018 · John M. Wilson, Walker J. Turner, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 44
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects
2018 · Walker J. Turner, John W. Poulton, et al. · Custom Integrated Circuits Conference · 35
Reinforcement Learning Guided Detailed Routing for Custom Circuits
2023 · Hao Chen, Kai-Chieh Hsu, et al. · International Symposium on Physical Design · 32
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A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
2023 · Yoshinori Nishi, John W. Poulton, et al. · IEEE Journal of Solid-State Circuits · 25
A microfluidic wireless power system
2015 · N. Lazarus, C. D. Meyer, et al. · RSC Advances · 18
TAG: Learning Circuit Spatial Embedding from Layouts
2022 · Keren Zhu, Hao Chen, et al. · International Conference on Computer Aided Design · 17
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An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop
2022 · Nandish Mehta, Stephen G. Tell, et al. · IEEE Journal of Solid-State Circuits · 17
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS
2022 · Yoshinori Nishi, John W. Poulton, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 15
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET
2019 · Sanquan Song, John Poulton, et al. · Custom Integrated Circuits Conference · 12
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
2023 · Yoshinori Nishi, John W. Poulton, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 10
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies
2022 · Hao Chen, Walker J. Turner, et al. · International Symposium on Physical Design · 9
Ground-Referenced Single-Ended Signaling: Applications for High-Density, Short-Haul Communication Systems
2019 · John M. Wilson, Walker J. Turner, et al. · IEEE Solid-State Circuits Magazine · 9
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links
2020 · Xi Chen, Nikola Nedovic, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 8
Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications
2024 · Walker J. Turner, John W. Poulton, et al. · Custom Integrated Circuits Conference · 7
Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories
2022 · Hao Chen, Walker J. Turner, et al. · Design, Automation, and Test in Europe · 6
A 4.7 T/11.1 T NMR Compliant 50 nW Wirelessly Programmable Implant for Bioartificial Pancreas In Vivo Monitoring
2016 · Walker J. Turner, Rizwan Bashirullah · IEEE Journal of Solid-State Circuits · 5
A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop
2021 · Nandish Mehta, Stephen Tell, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 4
Nuclear magnetic resonance energy harvesting for ultra-low power biomedical implants
2011 · Walker Turner, Chun-Ming Tang, et al. · The ... IEEE Annual Wireless and Microwave Technology Conference · 4
ChipVQA: Benchmarking Visual Language Models for Chip Design
2025 · Haoyu Yang, Qijing Huang, et al. · Design, Automation, and Test in Europe · 1
A 4.7T/11.1T NMR compliant wirelessly programmable implant for bio-artificial pancreas in vivo monitoring
2014 · Walker J. Turner, Rizwan Bashirullah · Symposium on VLSI Circuits · 1
A Tissue Equivalent Phantom of the Human Torso for in vivo Biocompatible Communications
2010 · David M. Peterson, Walker Turner, et al. · World Congress on Medical Physics and Biomedical Engineering, September 7 - 12, 2009, Munich, Germany · 1
Works count: 26
Citation count: 595
H-index: 12
I10-index: 14
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