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İsmail Emir Yüksel

Observed names: ISmail Emir Yüksel, Ismail E. Yuksel, Ismail Emir Yuksel, Ismail Emir Yüksel, Yuksel, Ismail Emir, Yüksel, Ismail Emir, Yüksel, İsmail Emir, ismail Emir Yüksel
Institution: ETH Zurich
ORCID: 0000-0003-3310-4423
Observed ORCID: 0000-0003-3310-4423
OpenAlex ID: A5041744643
An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration
2020 · Behzad Salami, Erhan Baturay Onural, et al. · International Conference on Dependable Systems & Networks/Proceedings · 57
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Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis
2024 · İsmail Emir Yüksel, Yahya Can Tuğrul, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 34
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Memory-Centric Computing: Solving Computing’s Memory Problem
2025 · Onur Mutlu, Ataberk Olgun, et al. · IEEE International Memory Workshop (IMW) · 32
CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost
2024 · F. Nisa Bostanci, ISmail Emir Yüksel, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 29
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BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads
2024 · Oğuzhan Canpolat, A. Giray Yağlıkçı, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 28
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Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance
2025 · Oğuzhan Canpolat, A. Giray Yağlıkçı, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 26
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Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
2024 · Abdullah Giray Yağlıkçı, Yahya Can Tuğrul, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 25
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Memory-Centric Computing: Recent Advances in Processing-in-DRAM (Invited)
2024 · Onur Mutlu, Ataberk Olgun, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 20
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Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis
2024 · İsmail Emir Yüksel, Yahya Can Tuğrul, et al. · International Conference on Dependable Systems & Networks/Proceedings · 19
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ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems
2025 · Ismail Emir Yuksel, Ataberk Olgun, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 18
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Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance
2025 · Ataberk Olgun, F. Nisa Bostancı, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 15
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An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips
2024 · Haocong Luo, İsmail Emir Yüksel, et al. · IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S) · 15
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ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation
2023 · Olgun, Ataberk, Tugrul, Yahya Can, et al. · arXiv (Cornell University) · 15
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PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips
2023 · Yuksel, Ismail Emir, Tugrul, Yahya Can, et al. · arXiv (Cornell University) · 11
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Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies
2025 · Haocong Luo, İsmail Emir Yüksel, et al. · IEEE VLSI Test Symposium (VTS) · 10
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Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory
2025 · F. Nisa Bostancı, Konstantinos Kanellopoulos, et al. · International Conference on Dependable Systems & Networks/Proceedings · 9
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Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
2025 · Yahya Can Tuğrul, A. Giray Yağlıkçı, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 9
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MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs
2021 · Ismail Emir Yuksel, Behzad Salami, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 9
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Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses
2025 · F. Nisa Bostancı, Oğuzhan Canpolat, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 7
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PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips
2025 · Ismail Emir Yuksel, Akash Sood, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 7
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TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs
2022 · Yüksel, İsmail Emir, Olgun, Ataberk, et al. · arXiv (Cornell University) · 5
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In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips
2025 · ismail Emir Yüksel, Ataberk Olgun, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 4
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Harmonia: Enhancing Data Placement and Migration in Hybrid Storage Systems via Multi-Agent Reinforcement Learning
2026 · Rakesh Nadig, Vamanan Arulchelvan, et al. · International Conference on Supercomputing · 3
Demonstrating Reduced-Voltage FPGA-Based Neural Network Acceleration for Power-Efficiency
2020 · Erhan Baturay Onural, Ismail Emir Yuksel, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 3
Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding
2026 · Daichi Tokuda, Tatsuya Kubo, et al. · International Conference on Supercomputing · 2
Works count: 59
Citation count: 428
H-index: 13
I10-index: 15
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