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Kosuke Hatsuda

Observed name: K. Hatsuda
OpenAlex ID: A5042713853
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes
2010 · Hidehiro Shiga, Daisaburo Takashima, et al. · IEEE Journal of Solid-State Circuits · 77
Floating Body RAM Technology and its Scalability to 32nm Node and Beyond
2006 · Tomoaki Shino, Naoki Kusunoki, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 33
A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability
2007 · Takeshi Hamamoto, Yoshihiro Minami, et al. · IEEE Transactions on Electron Devices · 27
First demonstration of full integration and characterization of 4F² 1S1M cells with 45 nm of pitch and 20 nm of MTJ size
2022 · Soo Man Seo, Hisanori Aikawa, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 23
Design of a 128-Mb SOI DRAM Using the Floating Body Cell (FBC)
2005 · T. Ohsawa, K. Fujita, et al. · IEEE Journal of Solid-State Circuits · 21
A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance
2010 · Daisaburo Takashima, Yasushi Nagadomi, et al. · IEEE Journal of Solid-State Circuits · 19
A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes
2009 · H. Shiga, D. Takashima, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 19
An 18.5ns 128Mb SOI DRAM with a floating body cell
2005 · T. Ohsawa, K. Fujita, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 19
A 128Mb Floating Body RAM(FBRAM) on SOI with Multi-Averaging Scheme of Dummy Cell
2006 · T. Ohsawa, T. Higashi, et al. · Symposium on VLSI Circuits · 15
Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells
2011 · Takashi Ohsawa, Kosuke Hatsuda, et al. · IEEE Journal of Solid-State Circuits · 14
30.6 A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a .001681\mu\mathrm{m}$ 1T-1MTJ Cross-Point Cell
2025 · Kosuke Hatsuda, Katsuhiko Hoya, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 13
FBC's Potential of 6F2 Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin
2007 · Fumiyoshi Matsuoka, Takashi Ohsawa, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 12
A 333MHz random cycle DRAM using the floating body cell
2006 · K. Hatsuda, K. Fujita, et al. · Custom Integrated Circuits Conference · 12
A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM
2006 · Y. Minami, T. Shino, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Reliable Memory Operation with Low Read Disturb Rate in the World Smallest 1Selector-1MTJ Cell for 64 Gb Cross-Point MRAM
2024 · Hisanori Aikawa, Jeonghwan Song, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 6
A perspective on NVRAM technology for future computing system
2019 · Katsuhiko Hoya, Kosuke Hatsuda, et al. · International Symposium on VLSI Design, Automation and Test · 5
A perspective on NVRAM technology for future computing system
2019 · Katsuhiko Hoya, Kosuke Hatsuda, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 3
A 128Mb ChainFeRAMTM and system designs for HDD application and enhanced HDD performance
2009 · Daisaburo Takashima, Yasushi Nagadomi, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 3
A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology Node for Embedded Applications
2006 · T. Hamamoto, Y. Minami, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 2
Demonstration of reliable memory operation in the world’s smallest 1 Selector-1 MTJ cell
2025 · Kuniaki Sugiura, Hisanori Aikawa, et al. · IEEE Magnetic Recording Conference (TMRC)
Corrigendum: "Analysis of hot carrier instability in a floating body cell" [Jpn. J. Appl. Phys. 63, 094002 (2024)]
2024 · Hiroomi Nakajima, Tomoaki Shino, et al. · Japanese Journal of Applied Physics
Analysis of hot carrier instability in a floating body cell
2024 · Hiroomi Nakajima, Tomoaki Shino, et al. · Japanese Journal of Applied Physics
A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a
2007 · Soi Dram, Takeshi Hamamoto, et al.
Technology development of 128Mb-FBC(Floating Body Cell) Memory by 90nm node CMOS process
2006 · Hiroomi Nakajima, Y. Minami, et al. · IEICE Technical Report; IEICE Tech. Rep.
A 128Mb DRAM Using a 1T Gain Cell(FBC) on SOI
2005 · Takashi Ohsawa, K. Fujita, et al. · 電子情報通信学会技術研究報告. ICD, 集積回路
Works count: 25
Citation count: 330
H-index: 12
I10-index: 13
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