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Saheli Sarkhel

Observed names: S. Sarkhel, Saheli Sarkel, Sarkhel Saheli
ORCID: 0000-0001-6333-9069
Observed ORCID: 0000-0001-6333-9069
OpenAlex ID: A5043122336
Spatial Composition Grading of Binary Metal Alloy Gate Electrode for Short-Channel SOI/SON MOSFET Application
2012 · Bibhas Manna, Saheli Sarkhel, et al. · IEEE Transactions on Electron Devices · 71
Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor
2015 · Saheli Sarkhel, Navjeet Bagga, et al. · Journal of Computational Electronics · 35
3D Modelling and Performance Analysis of Dual Material Tri-Gate Tunnel Field Effect Transistor
2018 · Priyanka Saha, Saheli Sarkhel, et al. · IETE Technical Review · 20
Recent research trends in gate engineered tunnel FET for improved current behavior by subduing the ambipolar effects: A review
2015 · Navjeet Bagga, Saheli Sarkhel, et al. · International Conference on Computing, Communication and Automation · 19
A compact quasi 3D threshold voltage modeling and performance analysis of a novel linearly graded binary metal alloy quadruple gate MOSFET for subdued short channel effects
2015 · Saheli Sarkhel, Subir Kumar Sarkar · Superlattices and Microstructures · 18
MoS 2 -Based Dual-Gate mosfet as Ultrasensitive SARs-CoV-2 Biosensor for Rapid Screening of Respiratory Syndrome
2023 · Rittik Ghosh, Saheli Sarkhel, et al. · IEEE Sensors Letters · 12
A comprehensive two dimensional analytical study of a nanoscale linearly graded binary metal alloy gate cylindrical junctionless MOSFET for improved short channel performance
2014 · Saheli Sarkhel, Subir Kumar Sarkar · Journal of Computational Electronics · 12
Compact 2D threshold voltage modeling and performance analysis of ternary metal alloy work-function-engineered double-gate MOSFET
2017 · Priyanka Saha, Saheli Sarkhel, et al. · Journal of Computational Electronics · 11
Analytical modeling and simulation of a linearly graded binary metal alloy gate nanoscale cylindrical MOSFET for reduced short channel effects
2014 · Saheli Sarkhel, Bibhas Manna, et al. · Journal of Computational Electronics · 11
L-Shaped Double Gate Bipolar Impact Ionization MOSFET Based Energy Efficient Leaky Integrate and Fire Neuron for Spiking Neural Network
2023 · Saheli Sarkhel, Tripty Kumari, et al. · IEEE Transactions on Nanotechnology · 10
A compact analytical model of binary metal alloy silicon-on-nothing (BMASON) tunnel FET with interface trapped charges
2017 · Saheli Sarkhel, Navjeet Bagga, et al. · Journal of Computational Electronics · 8
A 588 nW , 1 nA current reference circuit with extremely low (0.002%/V) line sensitivity over a wide supply voltage range and low temperature coefficient
2022 · Koyel Mukherjee, Trisha Sau, et al. · International Journal of Numerical Modelling Electronic Networks Devices and Fields · 7
Exploring the Asymmetric Characteristics of a Double Gate MOSFET with Linearly Graded Binary Metal Alloy Gate Electrode for Enhanced Performance
2016 · Navjeet Bagga, Saheli Sarkhel, et al. · IETE Journal of Research · 7
Two-Dimensional Potential and Threshold Voltage Modeling of Work Function Engineered Double Gate High-k Gate Stack Schottky Barrier MOSFET
2019 · Priyanka Saha, Saheli Sarkhel, et al. · Journal of Electronic Materials · 6
A Compact Two Dimensional Analytical Modeling of Nanoscale Fully Depleted Dual Material Gate Strained SOI/SON MOSFETs for Subdued SCEs
2014 · Saheli Sarkhel, Bibhas Manna, et al. · Journal of Low Power Electronics · 5
Design and analysis of Z shaped InGa0.5As0.5/Si tunnel FET using non-equilibrium Green’s function model for hydrogen gas sensing application
2023 · Rittik Ghosh, Saheli Sarkhel, et al. · Micro and Nanostructures · 4
3D Modeling based Performance Analysis of Gate Engineered Trigate SON TFET with SiO2/HfO2 stacked gate oxide
2018 · Priyanka Saha, Saheli Sarkhel, et al. · IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) · 4
A two dimensional analytical modeling of fully depleted dual material gate SON MOSFET and evidence for suppressed SCEs
2012 · S. Naha, S. Sarkhel, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 4
An approach for modeling propagation delay of a subthreshold inverter incorporating DIBL effect
2023 · Ilika Mitra, Wasim Habib, et al. · Devices for Integrated Circuit (DevIC) · 3
A 0.6 V 1.6 nA Constant Current Reference Circuit with Improved Power Supply Sensitivity
2021 · Taha Saquib, Saheli Sarkhel, et al. · Devices for Integrated Circuit (DevIC) · 3
Exploring the Threshold Voltage Characteristics and Short Channel Behavior of Gate Engineered Front Gate Stack MOSFET with Graded Channel
2018 · Saheli Sarkhel, Priyanka Saha, et al. · Silicon · 2
Analytical Modeling and Performance Characterization of a Double Gate MOSFET with Dielectric Pockets Incorporating Work Function Engineered Binary Metal Alloy Gate Electrode for Subdued SCEs
2017 · Ranita Saha, Saheli Sarkhel, et al. · IETE Technical Review · 2
Realization of gate performance using hybrid SET-CMOS pass transistor based logic gate
2013 · Anindya Jana, Kousik Naskar, et al. · Annual International Conference on Emerging Research Areas and International Conference on Microelectronics, Communications and Renewable Energy · 2
InAs/Si based Heterojunction TFET as improved in-situ breast cancer biomarker (C-erbB-2) detector
2025 · Nayanika Mukherjee, Deepraj Chakraborty, et al. · Devices for Integrated Circuit (DevIC) · 1
Investigation of geometrical impact on a P+ buried negative capacitance SOI FET
2022 · Toushik Santra, Ankit Dixit, et al. · Microelectronics Journal · 1
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Works count: 53
Citation count: 289
H-index: 10
I10-index: 10
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