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Yen-Huei Chen

ORCID: 0000-0002-9254-5256
Observed ORCID: 0000-0002-9254-5256
OpenAlex ID: A5043405308
16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications
2021 · Yu-Der Chih, Po-Hao Lee, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 405
A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations
2022 · Hidehiro Fujiwara, Haruki Mori, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 246
A 16 nm 128 Mb SRAM in High-$\kappa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications
2014 · Yen-Huei Chen, Wei-Min Chan, et al. · IEEE Journal of Solid-State Circuits · 137
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update
2023 · Haruki Mori, Wei-Chang Zhao, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 119
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm 2 and 3.78Mb/mm 2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell
2024 · Hidehiro Fujiwara, Haruki Mori, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 79
12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications
2017 · Jonathan Chang, Yen-Huei Chen, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 75
A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme
2011 · Jui-Jen Wu, Yen-Huei Chen, et al. · IEEE Journal of Solid-State Circuits · 75
A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications
2013 · J. Chang, Yen-Huei Chen, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 69
15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V MIN Applications
2020 · Jonathan Chang, Yen-Huei Chen, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 51
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V MIN Applications
2020 · Tsung-Yung Jonathan Chang, Yen-Huei Chen, et al. · IEEE Journal of Solid-State Circuits · 37
A large σVTH/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme
2010 · Jui-Jen Wu, Yen-Huei Chen, et al. · Symposium on VLSI Circuits · 29
24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue
2019 · Hidehiro Fujiwara, Chih-Yu Lin, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 20
A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications
2016 · Hidehiro Fujiwara, Yen-Huei Chen, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 19
Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM
2012 · Yen-Huei Chen, Shao-Yu Chou, et al. · IEEE Journal of Solid-State Circuits · 16
A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute
2025 · Tsung-Yung Jonathan Chang, Yen-Huei Chen, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 15
A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications
2023 · Jonathan Chang, Yen-Huei Chen, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 15
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications
2016 · Yen-Huei Chen, Kao-Cheng Lin, et al. · Symposium on VLSI Circuits · 15
13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications
2014 · Yen-Huei Chen, Wei-Min Chan, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 15
A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms
2013 · Meng-Fan Chang, Chih-Sheng Lin, et al. · IEEE Journal of Solid-State Circuits · 15
A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms
2011 · Meng‐Fan Chang, Wei-Cheng Wu, et al. · Symposium on VLSI Circuits · 13
Embedded memories for mobile, IoT, automotive and high performance computing
2017 · Jonathan Chang, Hung-Jen Liao, et al. · Symposium on VLSI Technology · 10
17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies
2015 · Hidehiro Fujiwara, Li-Wen Wang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 10
24.4 A 5nm [email protected] and [email protected] 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue
2021 · Hidehiro Fujiwara, Yi-Hsin Nien, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 9
High-Speed Embedded Memory for AI and High-Performance Compute
2023 · Yih Wang, Yen-Huei Chen, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 8
A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm 2 -17 TFLOPS/mm 2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle
2025 · Haruki Mori, Je-Min Hung, et al. · IEEE Journal of Solid-State Circuits · 5
Works count: 32
Citation count: 1,519
H-index: 15
I10-index: 22
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