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Hsiang-Yun Cheng

Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks
2019 · Tzu-Hsien Yang, Hsiang-Yun Cheng, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 159
Efficient and Robust Parallel DNN Training through Model Parallelism on Multi-GPU Platform
2018 · Chen, Chi-Chung, Yang, Chia-Lin, et al. · arXiv (Cornell University) · 124
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DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning
2018 · Meng-Yao Lin, Hsiang-Yun Cheng, et al. · 78
Memory Latency Reduction via Thread Throttling
2010 · Hsiang-Yun Cheng, Chung-Hsiang Lin, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 52
Core vs. uncore: the heart of darkness
2015 · Hsiang-Yun Cheng, Jia Zhan, et al. · ACM/IEEE Design Automation Conference (DAC) · 36
Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell
2016 · Meng-Fan Chang, Ching-Hao Chuang, et al. · IEEE International Symposium on Circuits and Systems proceedings · 30
RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration
2021 · Chen-Yang Tsai, Chin-Fu Nien, et al. · ACM/IEEE Design Automation Conference (DAC) · 26
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling
2017 · Li-Jhan Chen, Hsiang-Yun Cheng, et al. · IEEE Computer Architecture Letters · 20
LAP: loop-block aware inclusion properties for energy-efficient asymmetric last level caches
2016 · Hsiang-Yun Cheng, Jishen Zhao, et al. · ACM SIGARCH Computer Architecture News · 19
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches
2016 · Hsiang-Yun Cheng, Jishen Zhao, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 16
TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration
2019 · Jing-Yuan Luo, Hsiang-Yun Cheng, et al. · IEEE Transactions on Computers · 15
DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators
2022 · Wei-Ting Lin, Hsiang-Yun Cheng, et al. · ACM Transactions on Embedded Computing Systems · 14
Future Computing Platform Design: A Cross-Layer Design Approach
2021 · Hsiang-Yun Cheng, Chun-Feng wu, et al. · Design, Automation, and Test in Europe · 14
ReAIM: A ReRAM-based Adaptive Ising Machine for Solving Combinatorial Optimization Problems
2024 · Hao-Wei Chiang, Chin-Fu Nien, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 12
Efficient Bad Block Management with Cluster Similarity
2022 · Jui-Nan Yen, Yao-Ching Hsieh, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 11
LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling
2018 · Ke, Zhi-Lin, Cheng, Hsiang-Yun, et al. · arXiv (Cornell University) · 9
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The Effect of Surfactant Content over Cu-Ni Coatings Electroplated by the sc-CO2 Technique
2017 · Ho-Chiao Chuang, Jorge Sánchez, et al. · Materials · 9
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EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors
2015 · Hsiang-Yun Cheng, Matt Poremba, et al. · ACM Transactions on Architecture and Code Optimization · 9
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EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors
2014 · Hsiang-Yun Cheng, Matt Poremba, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 8
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GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing
2020 · Chin-Fu Nien, Yi-Jou Hsiao, et al. · Design, Automation, and Test in Europe · 7
Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference
2015 · Hsiang-Yun Cheng, Mary Jane Irwin, et al. · ACM Transactions on Design Automation of Electronic Systems · 7
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Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications
2023 · Jorg Henkel, Lokesh Siddhu, et al. · International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · 6
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Tensor Movement Orchestration in Multi-GPU Training Systems
2023 · Shao-Fu Lin, Yi-Jung Chen, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 6
BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network
2024 · Chi-Tse Huang, Cheng-Yang Chang, et al. · Design, Automation, and Test in Europe · 5
This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator
2022 · Yen-Ting Tsou, Kuan-Hsun Chen, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 5
Works count: 48
Citation count: 731
H-index: 13
I10-index: 15
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