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Yun-Shiang Shu
Observed name:
Y.-S. Shu
Institution:
MediaTek (Taiwan)
Observed institutions:
MediaTek (China),
University of California San Diego,
MediaTek (Taiwan)
OpenAlex ID:
A5044134250
An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS
2016
·
Yun-Shiang Shu
, Liang-Ting Kuo
, et al.
·
IEEE Journal of Solid-State Circuits
·
196
A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering
2008
·
Yun-Shiang Shu
, Bang-Sup Song
·
IEEE Journal of Solid-State Circuits
·
116
26.1 A 4.5mm2 Multimodal Biosensing SoC for PPG, ECG, BIOZ and GSR Acquisition in Consumer Wearable Devices
2020
·
Yun-Shiang Shu
, Zhi-Xin Chen
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
109
A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators
2012
·
Yun-Shiang Shu
·
Symposium on VLSI Circuits
·
100
A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer
2013
·
Yun-Shiang Shu
, Jui-Yuan Tsai
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
64
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time $\Delta\Sigma$ Modulators
2010
·
Yun-Shiang Shu
, Junpei Kamiishi
, et al.
·
IEEE Journal of Solid-State Circuits
·
57
27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS
2016
·
Yun-Shiang Shu
, Liang-Ting Kuo
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
56
9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s
2020
·
Su-Hao Wu
, Yun-Shiang Shu
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
48
A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection
2008
·
Yun-Shiang Shu
, Bang-Sup Song
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
22
20.4 An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS
2019
·
Tien-Yu Lo
, Chan-Hsiang Weng
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
20
A 10$\sim$15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration
2009
·
Yun-Shiang Shu
, MoonJung Kyung
, et al.
·
IEEE Journal of Solid-State Circuits
·
13
An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range
2019
·
Wei-Hsiang Huang
, Su-Hao Wu
, et al.
·
Symposium on VLSI Circuits
·
9
24.6 A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC
2025
·
Cheng-En Hsieh
, Gabriele Manganaro
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
8
Design Techniques for High Linearity and Dynamic Range Digital to Analog Converters
2022
·
Ayman Shabra
, Yun-Shiang Shu
, et al.
·
Custom Integrated Circuits Conference
·
7
A self-calibrated 2–1–1 cascaded continuous-time ΔΣ modulator
2009
·
Junpei Kamiishi
, Yun-Shiang Shu
, et al.
·
Custom Integrated Circuits Conference
·
6
A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration
2008
·
Yun-Shiang Shu
, Moon-Jung Kyung
, et al.
·
Custom Integrated Circuits Conference
·
6
A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring
2015
·
Liang-Ting Kuo
, Chun-Chih Hou
, et al.
·
IEEE Asian Solid-State Circuits Conference (A-SSCC)
·
4
Tutorial: Noise-Shaping SAR ADCs
2022
·
Yun-Shiang Shu
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
2
A Hybrid Architecture for a Reconfigurable SAR ADC
2017
·
Yun-Shiang Shu
, Liang-Ting Kuo
, et al.
·
Springer eBooks
·
2
Signal processing and analog/RF circuit design: cross-discipline interactions and technical challenges
2016
·
Yun-Shiang Shu
, Stacy Ho
, et al.
·
APSIPA Transactions on Signal and Information Processing
·
2
PDF
Introduction of Noise-Shaping SAR ADCs
2022
·
Yun-Shiang Shu
·
International Symposium on VLSI Design, Automation and Test
·
1
A background calibration technique for fully dynamic flash ADCs
2013
·
Yun-Shiang Shu
, Jui-Yuan Tsai
, et al.
·
International Symposium on VLSI Design, Automation and Test
·
1
F2: Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits
2021
·
Youngcheol Chae
, Yun-Shiang Shu
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
PDF
Circuits evening panel discussion 2: Wearable electronics: Still an oasis or just a mirage for the semiconductor industry?
2015
·
Y.-S. Shu
, N. Verma
, et al.
·
Symposium on VLSI Circuits
Background digital calibration techniques for high-speed, high resolution analog-to-digital data converters
2008
·
Yun-Shiang Shu
·
eScholarship (California Digital Library)
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Works count:
25
Citation count:
849
H-index:
11
I10-index:
11
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