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Satish S. Bhairannawar

Observed names: Sathish Bhairannawar, Satish Bhairannawar, Satish S Bhairannawar, Satish s Bhairannawar
ORCID: 0000-0002-2576-5590
Observed ORCID: 0000-0002-2576-5590
OpenAlex ID: A5044309525
Efficient Medical Image Enhancement Technique Using Transform HSV Space and Adaptive Histogram Equalization
2018 · Satish S. Bhairannawar · Elsevier eBooks · 37
Color image enhancement using Laplacian filter and contrast limited adaptive histogram equalization
2017 · Satish Bhairannawar, Apeksha Patil, et al. · Innovations in Power and Advanced Computing Technologies (i-PACT) · 27
Implementation of Fingerprint Based Biometric System Using Optimized 5/3 DWT Architecture and Modified CORDIC Based FFT
2017 · Satish S. Bhairannawar, Sayantam Sarkar, et al. · Circuits Systems and Signal Processing · 20
Plant Leaf Disease Classification Using Modified SVM With Post Processing Techniques
2023 · R Thyagaraj., T.Y Satheesha, et al. · International Conference on Applied Intelligence and Sustainable Computing (ICAISC) · 19
Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications
2021 · Sayantam Sarkar, Satish S. Bhairannawar · Multidimensional Systems and Signal Processing · 19
Design and Implementation of High Speed Background Subtraction Algorithm for Moving Object Detection
2016 · Sunanda R. Hanchinamani, Sayantam Sarkar, et al. · Procedia Computer Science · 17
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EEG Classification Using Modified KNN Algorithm
2023 · B M Thejaswini, T Y Satheesha, et al. · International Conference on Applied Intelligence and Sustainable Computing (ICAISC) · 15
FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing
2021 · Sayantam Sarkar, Satish S. Bhairannawar, et al. · IET Circuits Devices & Systems · 14
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Chili Disease Detection and Classification using Various Machine Learning Techniques
2023 · Yashodha Sambrani, Rajashekarappa, et al. · International Conference on Applied Intelligence and Sustainable Computing (ICAISC) · 11
FPGA Implementation of Moving Object and Face Detection Using Adaptive Threshold
2015 · Sateesh Kumar H.C, Sayantam Sarkar, et al. · International Journal of VLSI Design & Communication Systems · 11
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FPGA Implementation of Optimized Karhunen–Loeve Transform for Image Processing Applications
2018 · Satish S. Bhairannawar, Sayantam Sarkar, et al. · Journal of Real-Time Image Processing · 9
An efficient VLSI architecture for fingerprint recognition using O2D-DWT architecture and modified CORDIC-FFT
2015 · Satish S Bhairannawar, Sayantam Sarkar, et al. · IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES) · 9
Computer Game-Based Telerehabilitation Platform Targeting Manual Dexterity: Exercise Is Fun. “You Are Kidding—Right?”
2021 · Sanjay Tejraj Parmar, Anuprita Kanitkar, et al. · Sensors · 8
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An Efficient Reconfigurable Architecture for Fingerprint Recognition
2016 · Satish S. Bhairannawar, K. B. Raja, et al. · VLSI design · 6
An Adaptive Threshold based FPGA Implementation for Object and Face detection
2015 · Sateesh Kumar H.C., Sayantam Sarkar, et al. · International Conference on Image Information Processing (ICIIP) · 6
FPGA implementation of high speed Vedic multiplier using CSLA for parallel FIR architecture
2014 · S. Amina Naaz, M. N. Pradeep, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 6
Efficient reconfigurable architecture to extract image features for face recognition using local binary pattern
2025 · Sumangala Bhavikatti, Satish Bhairannawar · Soft Computing · 5
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FPGA Based Efficient Multiplier for Image Processing Applications Using Recursive Error Free Mitchell Log Multiplier and KOM Architecture
2014 · Satish S Bhairannawar, Rathan R, et al. · International Journal of VLSI Design & Communication Systems · 5
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FPGA based Recursive Error Free Mitchell Log Multiplier for image Filters
2012 · Satish S Bhairannawar, R Rathan, et al. · IEEE International Conference on Computational Intelligence and Computing Research (ICCIC) · 5
Efficient reconfigurable architecture to enhance medical image security
2023 · Prakash Marakumbi, Satish Bhairannawar · Indonesian Journal of Electrical Engineering and Computer Science · 3
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Efficient de-noising technique for electroencephalogram signal processing
2022 · Virupaxi Dalal, Satish Bhairannawar · IAES International Journal of Artificial Intelligence · 3
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Efficient FPGA architecture to implement non-separable fast Fourier transform for image and video applications
2022 · Sayantam Sarkar, Satish S. Bhairannawar · International Journal of Electronics · 3
FPGA implementation of face recognition system using efficient 5/3 2D-lifting scheme
2016 · Satish S Bhairannawar, Rajath Kumar, et al. · IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA) · 3
FPGA Implementation of Fingerprint Recognition System using Adaptive Threshold Technique
2015 · Satish S Bhairannawar, Anand R, et al. · International Conference on Electrical, Electronics, Signals, Communication and Optimization · 3
An efficient controller-based architecture for AES algorithm using FPGA
2024 · Reshma Nadaf, Satish S. Bhairannawar · Indonesian Journal of Electrical Engineering and Computer Science · 2
Works count: 36
Citation count: 271
H-index: 10
I10-index: 10
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