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Nilesh Patidar
Observed institution:
Shri Vaishnav Vidyapeeth Vishwavidyalaya, Indore
ORCID:
0000-0001-8712-5938
Observed ORCID:
0000-0001-8712-5938
OpenAlex ID:
A5044544351
Efficient designs of high-speed combinational circuits and optimal solutions using 45-degree cell orientation in QCA nanotechnology
2022
·
Arpita Tiwari
, Mukesh Patidar
, et al.
·
Materials Today Proceedings
·
17
An ultra-dense and cost-efficient coplanar RAM cell design in quantum-dot cellular automata technology
2023
·
Mukesh Patidar
, Ankit Jain
, et al.
·
The Journal of Supercomputing
·
12
An extensible architecture of 32-bit ALU for high-speed computing in QCA technology
2022
·
Nilesh Patidar
, Namit Gupta
·
The Journal of Supercomputing
·
10
Design of Hybrid Adder-Subtractor (HAS) using Reversible Logic Gates in QCA
2012
·
Namit Gupta
, Nilesh Patidar
, et al.
·
International Journal of Computer Applications
·
6
PDF
Error Detection in 2-bit and 4-bit Multiplier using Parity Predictor Circuit in QCA
2015
·
Ankita Laad
, Namit Gupta
, et al.
·
International Journal of Computer Applications
·
4
PDF
The Role of Nanoelectronic Devices in a Smart City Ecosystem
2022
·
Mukesh Patidar
, Namit Gupta
, et al.
·
CRC Press eBooks
·
2
An Efficient Layout of Single-Layer Full Adder Using QCA
2020
·
Nilesh Patidar
, Namit Gupta
·
Advances in intelligent systems and computing
·
2
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Works count:
8
Citation count:
53
H-index:
4
I10-index:
3
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