Author

Nameirakpam Basanta Singh

Observed names: Basanta Singh Nameriakpam, N B Singh, N Basanta Singh, N. B. Singh, N. BASANTA SINGH, N. Basanta Singh, N. Singh, N.B. Singh, N.Basanta Singh

Institution: Manipur University

Observed institutions: Manipur University, University of Mumbai, Jadavpur University, Kurukshetra University, Council for Scientific and Industrial Research, National Institute of Technology Manipur, Central Electronics Engineering Research Institute, Massachusetts Institute of Technology, Council of Scientific and Industrial Research

ORCID: 0000-0001-6037-6593

Observed ORCID: 0000-0001-6037-6593

OpenAlex ID: A5044734998

Work Function Engineering With Linearly Graded Binary Metal Alloy Gate Electrode for Short-Channel SOI MOSFET

2011 · Sanjoy Deb, N. Basanta Singh, et al. · IEEE Transactions on Nanotechnology · 77

Design and simulation of hybrid CMOS–SET circuits

2012 · Anindya Jana, N. Basanta Singh, et al. · Microelectronics Reliability · 27

Artificial Neural Network Approach for More Accurate Solar Cell Electrical Circuit Model

2014 · Khomdram Jolson Singh, K L Rita Kho, et al. · International Journal on Computational Science & Applications · 23

A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs

2011 · Sanjoy Deb, Saptarsi Ghosh, et al. · Journal of Semiconductors · 23

A modified macro model approach for SPICE based simulation of single electron transistor

2016 · Arpita Ghosh, Amit Jain, et al. · Journal of Computational Electronics · 20

A new SPICE macro model of single electron transistor for efficient simulation of single-electronics circuits

2015 · Amit Jain, Arpita Ghosh, et al. · Analog Integrated Circuits and Signal Processing · 20

Analytical model of threshold voltage and sub-threshold slope of SOI and SON MOSFET: A comparative study

2011 · Subir Kumar Sarkar, Sanjoy Deb, et al. · Materials science : an Indian journal · 14

Stability and Reliability Analysis of Hybrid CMOS-SET Circuits—A New Approach

2014 · Amit Jain, Arpita Ghosh, et al. · Journal of Computational and Theoretical Nanoscience · 11

A new compact analytical model of single electron transistor for hybrid SET–MOS circuits

2014 · Amit Jain, Basanta Singh Nameriakpam, et al. · Solid-State Electronics · 10

Textured window with DLAR coating design for an effective minimization of electrical and optical losses in an efficient III–V solar cell

2014 · Khomdram Jolson Singh, N. Basanta Singh, et al. · Journal of Computational Electronics · 9

Design and implementation of SET-CMOS hybrid half subtractor

2014 · Arpita Ghosh, Amit Jain, et al. · IEEE India Conference · 9

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

2011 · Sanjoy Deb, N. Basanta Singh, et al. · International Journal of Electronics · 8

Stability aspects of single electron threshold logic based 4 bit carry look ahead adder

2015 · Arpita Ghosh, Amit Jain, et al. · International Conference on Computer, Communication, Control and Information Technology · 6

Reliability Aspects and Performance Analysis of Single Electron Threshold Logic Based Programmable Logic Array

2015 · Arpita Ghosh, Amit Jain, et al. · Journal of Computational and Theoretical Nanoscience · 5

Examining the Short Channel Characteristic and Performance of Triple Material Double Gate Silicon-on-Nothing Metal Oxide Semiconductor Field Effect Transistors with Grading Channel Concentration

2019 · Ningombam Ajit Kumar, Aheibam Dinamani Singh, et al. · Journal of Nanoelectronics and Optoelectronics · 4

Modeling and performance analysis of high-k gate material-based isfet biosensors using TCAD

2025 · Phuritshabam Zenita, A. Balarampyari Devi, et al. · Journal of Computational Electronics · 3

Analysis of Harmonic Generated by Household Electronic Equipments with SMPS Using Matlab® Simulink®

2024 · Ayekpam Jagadananda, Lourembam Lastrong Mangang, et al. · International Conference on Energy, Power and Environment (ICEPE) · 3

Single electron threshold logic based Feynman gate implementation

2016 · Arpita Ghosh, Amit Jain, et al. · International Conference on Research in Computational Intelligence and Communication Networks (ICRCICN) · 3

Techniques of image segmentation: a review

2025 · Sharmila Meinam, Kishorjit Nongmeikapam, et al. · Indonesian Journal of Electrical Engineering and Computer Science · 2

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High frequency analytical modelling and performance comparison of nanoscale SOI MOS structures

2018 · C. Rajarajachozhan, Nameirakpam Basanta Singh, et al. · International Journal of Electronics · 2

Error probability independent delay analysis of single electronics circuits

2017 · Amit Jain, Arpita Ghosh, et al. · International Journal of Circuit Theory and Applications · 2

Implementation Aspects of Logic Functions using Single Electron Threshold Logic Gates and Hybrid SET-MOS Circuits

2015 · Amit Jain, Arpita Ghosh, et al. · IETE Journal of Research · 2

A Comparative Study of Single Electron Threshold Logic-Based and SET-MOS Hybrid Based Half Subtractor

2015 · Arpita Ghosh, Amit Jain, et al. · Lecture notes in electrical engineering · 2

3D Single Gaas Co-Axial Nanowire Solar Cell for Nanopillar-Array Photovoltaic Device

2014 · Khomdram Jolson Singh, Chelsea Leiphrakpam, et al. · International Journal on Computational Science & Applications · 2

Particle swarm approach for parameter optimization of quantum well nano structure

2011 · Sanjoy Deb, N. Basanta Singh, et al. · Expert Systems with Applications · 2

Works count: 56

Citation count: 298

H-index: 9

I10-index: 9