Get started
Author

Dheeraj Singh Rajput

Observed names: Dheeraj Singh Rajpiut, Rajput, Dheeraj Singh
ORCID: 0000-0002-5608-1511
Observed ORCID: 0000-0002-5608-1511
OpenAlex ID: A5045062034
Audio Compression Algorithm using Discrete Cosine Transform (DCT) and Lempel-Ziv-Welch (LZW) Encoding Method
2019 · Sankalp Shukla, Maniram Ahirwar, et al. · International Conference on Machine Learning, Big Data, Cloud and Parallel Computing (COM-IT-CON) · 12
Optimization of performance parameters of differential ring oscillator using Taguchi DoE and Pareto ANOVA techniques for fast-setting PLL frequency synthesizer
2025 · Archana Singhal, Jyoti Sharma, et al. · Analog Integrated Circuits and Signal Processing · 8
Timer circuit using OTRA and its application as astable and Monostable multivibrator
2015 · Dheeraj Singh Rajput, Rohit Singh · International Conference on Electronics and Communication Systems (ICECS) · 8
An efficient race-free dynamic MCML design for multistage applications
2025 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · Analog Integrated Circuits and Signal Processing · 4
Analysis, Design and Optimization of Current Mode Logic: A State-of-the-art Review
2025 · Ruchi Bhaskar, Bharat Choudhary, et al. · IETE Technical Review · 4
Design and Analysis of Fast Settling Wideband PLL Using a Novel Low Mismatch Current Charge Pump
2024 · Archana Singhal, Jyoti Sharma, et al. · IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems · 4
Design and optimization of a Quad-Tail-Cell dynamic MCML for low-power three-input logic using Taguchi and ANOVA methods
2025 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · Analog Integrated Circuits and Signal Processing · 3
Improved MOS Current Mode Logic based Tri-state Buffer using DTMOS and its Applications
2025 · Ruchi Bhaskar, Bharat Choudhary, et al. · IEEE Open Conference of Electrical, Electronic and Information Sciences (eStream) · 3
Improved Positive Feedback Source Coupled Logic Based Tri-State Buffer and Its Applications
2025 · Ruchi Bhaskar, Bharat Choudhary, et al. · International Conference on Device Intelligence, Computing and Communication Technologies (DICCT) · 3
A Comparative Analysis of Lossless Compression Algorithms on Uniformly Quantized Audio Signals
2022 · Sankalp Shukla, Ritu Gupta, et al. · International Journal of Image Graphics and Signal Processing · 3
PDF
Controlling Ambipolar Current and Enhancement of On-state Current With High and Low Concentration Source Pockets
2022 · Sudhan Kumar, Dheeraj Singh Rajput, et al. · ICTACT Journal on Microelectronics · 2
Design and optimization of a low-power dynamic MCML-based phase-frequency detector using Taguchi DoE and ANOVA for frequency synthesizers with fast-locking of 0.5 μs
2026 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · AEU - International Journal of Electronics and Communications · 1
Design and Analysis of PVT Tolerant and Fast-Settling Wideband CP-PLL Frequency Synthesizer
2025 · Archana Singhal, Dheeraj Singh Rajput, et al. · International Conference on Device Intelligence, Computing and Communication Technologies (DICCT) · 1
Pulse Width Modulator Using Otra Based Timer Circuit
2022 · Dheeraj Singh Rajput, Ritu Gupta, et al. · ICTACT Journal on Microelectronics · 1
Optimization of Performance of Novel Quad Tail Cell Dynamic PFSCL Design Using Statistical Techniques for Low-Power Three-Input Logic Applications
2026 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · Circuits Systems and Signal Processing
Correction: Optimization of novel DPTL-PFD design for fast-settling PLL frequency synthesizer using Taguchi–ANOVA
2026 · Archana Singhal, Jyoti Sharma, et al. · Analog Integrated Circuits and Signal Processing
PDF
Improved Race-Free Cascaded Dynamic PFSCL Technique for Multistage Applications
2026 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · Circuits Systems and Signal Processing
A Low-Phase Noise, Low-Power PFD Circuit Using GDI and Pass Transistor Logic with PVT tolerance
2026 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · International Conference on Consumer Electronics
Optimization of novel DPTL-PFD design for fast-settling PLL frequency synthesizer using Taguchi–ANOVA
2026 · Archana Singhal, Jyoti Sharma, et al. · Analog Integrated Circuits and Signal Processing
Power-Efficient and High-Speed Dynamic MCML XOR Gate Using Triple-Tail Cells Architecture
2026 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · Lecture notes in electrical engineering
Design and Analysis of a GHz PLL Using GDI and Pass Transistor Based PFD with a Lock Time of 520 ns
2025 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · IEEE International Symposium on Smart Electronic Systems (iSES)
Design of Wideband, Low Phase Noise 3-Stage and 5-Stage Differential Ring VCOs for Wireless Communication Systems
2025 · Archana Singhal, Dheeraj Singh Rajput, et al. · IEEE International Symposium on Smart Electronic Systems (iSES)
Development of Generic Custom FILL Parameterized Cell
2025 · Tanu Shree Gothwal, Bharat Choudhary, et al. · International Conference on Device Intelligence, Computing and Communication Technologies (DICCT)
5G Wireless Communication and Its Adverse Effects on the Human Body: Distinguishing Falsehoods from Reality
2023 · Bale, Ajay Sudhir, Soni, Sabhyata Uppal, et al. · International Journal of Intelligent Systems and Applications in Engineering
PDF
Self-assessing processes in HPC applications: Alternate approach to Master/Slave Processes
2017 · Sankalp Shukla, Dheeraj Singh Rajput, et al. · International Conference on Innovative Mechanisms for Industry Applications
Works count: 25
Citation count: 57
H-index: 4
I10-index: 1
Year
Topic
Type