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Anton Tšertov

Observed names: A. Chertov, A. Tsertov, Anton Tsertov, Tsertov, Anton, Tšertov, Anton
ORCID: 0000-0003-4084-7313
Observed ORCID: 0000-0003-4084-7313
OpenAlex ID: A5045334611
A suite of IEEE 1687 benchmark networks
2016 · Anton Tsertov, Artur Jutman, et al. · IEEE International Test Conference (ITC) · 47
High-level modeling and testing of multiple control faults in digital systems
2016 · Artjom Jasnetski, Stephen Adeboye Oyeniran, et al. · IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) · 12
Software-based self-test generation for microprocessors with high-level decision diagrams
2014 · Raimund Ubar, Anton Tsertov, et al. · IEEE Latin American Test Symposium (LATS) · 11
Calculation of LFSR Seed and Polynomial Pair for BIST Applications
2008 · A. Jutman, A. Tsertov, et al. · IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) · 10
Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks
2019 · Aleksa Damljanovic, Artur Jutman, et al. · IEEE European Test Symposium (ETS) · 9
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On-Chip Sensors Data Collection and Analysis for SoC Health Management
2023 · Konstantin Shibin, Maksim Jenihhin, et al. · Proceedings · 6
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IEEE 1687 Compliant Ecosystem for Embedded Instrumentation Access and In-Field Health Monitoring
2018 · Anton Tsertov, Artur Jutman, et al. · IEEE AUTOTESTCON (IEEE Systems Readiness Technology Conference) · 6
Automated software-based self-test generation for microprocessors
2017 · Artjom Jasnetski, Raimund Ubar, et al. · International Conference Mixed Design of Integrated Circuits and Systems · 6
On automatic software-based self-test program generation based on high-level decision diagrams
2016 · Artjom Jasnetski, Raimund Ubar, et al. · IEEE Latin American Test Symposium (LATS) · 6
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams
2015 · Artjom Jasnetski, Jaan Raik, et al. · IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) · 5
Software-based self-test generation for microprocessors with high-level decision diagrams; pp. 48–61
2014 · Artjom Jasnetski, Raimund Ubar, et al. · Proceedings of the Estonian Academy of Sciences · 5
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Microprocessor-based System Test using Debug Interface
2008 · Sergei Devadze, Artur Jutman, et al. · NORCHIP · 5
SoC and Board Modeling for Processor-Centric Board Testing
2011 · Anton Tsertov, Raimund Ubar, et al. · Euromicro Conference on Digital System Design (DSD) · 4
High-level test data generation for software-based self-test in microprocessors
2017 · Adeboye Stephen Oyeniran, Artjom Jasnetski, et al. · Mediterranean Conference on Embedded Computing (MECO) · 3
FPGA-controlled PCBA power-on self-test using processor's debug features
2016 · B. Du, E. Sanchez, et al. · IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) · 3
BIST analyzer: A training platform for SoC testing
2007 · A. Jutman, A. Tsertov, et al. · IEEE Frontiers in Education Conference (FIE) · 3
A Hierarchical Approach to Health Management in Heterogeneous Embedded Systems
2025 · Anton Tsertov, Konstantin Shibin, et al. · IEEE Nordic Circuits and Systems Conference (NorCAS) · 2
Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
2019 · Aleksa Damljanovic, Artur Jutman, et al. · IEEE International Test Conference (ITC) · 2
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Automatic SoC Level Test Path Synthesis Based on Partial Functional Models
2011 · Anton Tsertov, Raimund Ubar, et al. · Proceedings - Asian Test Symposium/Proceedings · 2
E-Learning Environment for WEB-Based Study of Testing
2010 · Raimund Ubar, Artur Jutman, et al. · 2
Teaching digital test with BIST analyzer
2008 · A. Jutman, A. Tsertov, et al. · EAEEIE Annual Conference (EAEEIE) · 2
VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability
2017 · Hollstein, Thomas, Raik, Jaan, et al. · IFIP advances in information and communication technology · 1
Laboratory framework TEAM for investigating the dependability issues of microprocessor systems
2014 · Artjom Jasnetski, Raimund Ubar, et al. · European Workshop on Microelectronics Education (EWME) · 1
A Tool for Advanced Learning of LFSR-Based Testing Principles
2006 · A. Jutman, A. Tsertov, et al. · Biennial Baltic Electronics Conference (BEC) · 1
Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs
2024 · Hardi Selg, Konstantin Shibin, et al. · Proceedings
Works count: 39
Citation count: 154
H-index: 6
I10-index: 4
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