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Hongyan Xia
Observed name:
Xia, Hongyan
Institution:
ARM (United Kingdom)
Observed institutions:
University of Cambridge,
ARM (United Kingdom)
ORCID:
0000-0002-8047-899X
Observed ORCID:
0000-0002-8047-899X
OpenAlex ID:
A5045554783
CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety
2019
·
Hongyan Xia
, Jonathan Woodruff
, et al.
·
IEEE/ACM International Symposium on Microarchitecture (MICRO)
·
68
PDF
Cornucopia: Temporal Safety for CHERI Heaps
2020
·
Nathaniel Wesley Filardo
, Brett F. Gutstein
, et al.
·
IEEE Symposium on Security and Privacy (S&P)
·
67
PDF
CHERI Concentrate: Practical Compressed Capabilities
2019
·
Jonathan Woodruff
, Alexandre Joannou
, et al.
·
IEEE Transactions on Computers
·
67
PDF
Efficient Tagged Memory
2017
·
Alexandre Joannou
, Jonathan Woodruff
, et al.
·
IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)
·
53
PDF
CHERIoT: Complete Memory Safety for Embedded Devices
2023
·
Saar Amar
, David Chisnall
, et al.
·
IEEE/ACM International Symposium on Microarchitecture (MICRO)
·
41
PDF
Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 6)
2017
·
Robert N. M. Watson
, Peter G. Neumann
, et al.
·
CL Technical Reports
·
37
Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 9)
2023
·
Robert N. M. Watson
, Peter G. Neumann
, et al.
·
CL Technical Reports
·
27
CheriRTOS: A Capability Model for Embedded Devices
2018
·
Hongyan Xia
, Jonathan Woodruff
, et al.
·
IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)
·
27
CHERIoT RTOS: An OS for Fine-Grained Memory-Safe Compartments on Low-Cost Embedded Devices
2025
·
Saar Amar
, Tony Chen
, et al.
·
ACM SIGOPS Symposium on Operating Systems Principles (SOSP)
·
15
Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 8)
2020
·
Robert N. M. Watson
, Peter G. Neumann
, et al.
·
CL Technical Reports
·
14
Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7)
2019
·
Robert N. M. Watson
, Peter G. Neumann
, et al.
·
CL Technical Reports
·
3
Research data supporting 'Cornucopia: Temporal Safety for CHERI Heaps'
2020
·
Filardo, Nathaniel
, Gutstein, Brett
, et al.
·
Apollo (University of Cambridge)
Research data supporting "CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety"
2019
·
Xia, Hongyan
, Woodruff, Jonathan
, et al.
·
Apollo (University of Cambridge)
Capability Memory Protection for Embedded Systems
2019
·
Xia, Hongyan
·
Apollo (University of Cambridge)
PDF
Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 5)
2016
·
Robert N. M. Watson
, Peter G. Neumann
, et al.
·
CL Technical Reports
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Works count:
17
Citation count:
422
H-index:
10
I10-index:
10
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