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Author

Eleena Mohapatra

Observed names: E Mohapatra, E. Mohapatra, Eleena Mohpatra, MOHAPATRA, ELEENA
Observed institutions: Queen's University Belfast, Indian Institute of Technology Kharagpur, Veer Surendra Sai University of Technology, Siksha O Anusandhan University, Biju Patnaik University of Technology, R.V. College of Engineering, Visvesvaraya Technological University
ORCID: 0000-0002-1444-0440
Observed ORCID: 0000-0002-1444-0440
OpenAlex ID: A5045938356
Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes
2021 · E. Mohapatra, T. P. Dash, et al. · SN Applied Sciences · 31
Strain-engineering in nanowire field-effect transistors at 3 nm technology node
2020 · Tara Prasanna Dash, Suprava Dey, et al. · Physica E Low-dimensional Systems and Nanostructures · 26
Strain induced variability study in Gate-All-Around vertically-stacked horizontal nanosheet transistors
2020 · E Mohapatra, T P Dash, et al. · Physica Scripta · 22
Vertically-Stacked Silicon Nanosheet Field Effect Transistors at 3nm Technology Nodes
2019 · T.P. Dash, S. Dey, et al. · Devices for Integrated Circuit (DevIC) · 20
Design and simulation of vertically-stacked nanowire transistors at 3 nm technology nodes
2019 · S Dey, J Jena, et al. · Physica Scripta · 16
Performance comparison of strained-SiGe and bulk-Si channel FinFETs at 7 nm technology node
2019 · T P Dash, S Dey, et al. · Journal of Micromechanics and Microengineering · 15
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Design and optimization of stress/strain in GAA nanosheet FETs for improved FOMs at sub-7 nm nodes
2023 · E Mohapatra, D Jena, et al. · Physica Scripta · 14
Strain-engineering in AlGaN/GaN HEMTs: impact of silicon nitride passivation layer on electrical performance
2021 · Sanghamitra Das, Tara Prasanna Dash, et al. · Physica Scripta · 12
FinFET-Based Inverter Design and Optimization at 7 Nm Technology Node
2022 · J. Jena, D. Jena, et al. · Silicon · 11
Stress-Induced Variability Studies in Tri-Gate FinFETs with Source/Drain Stressor at 7 nm Technology Nodes
2019 · T. P. Dash, J. Jena, et al. · Journal of Electronic Materials · 10
Performance and Opportunities of Gate-All-Around Vertically-Stacked Nanowire Transistors at 3nm Technology Nodes
2019 · S. Dey, T. P. Dash, et al. · Devices for Integrated Circuit (DevIC) · 9
Linearity improvement in graded channel AlGaN/GaN HEMTs for high-speed applications
2023 · Devika Jena, Sanghamitra Das, et al. · Physica Scripta · 8
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Toward Ultimate Scaling: From FinFETs to Nanosheet Transistors
2020 · T. P. Dash, E. Mohapatra, et al. · Lecture notes in networks and systems · 8
Deformation‐induced stress/strain mapping and performance evaluation of a‐IGZO thin‐film transistors for flexible electronic applications
2020 · Taraprasanna Dash, Eleena Mohapatra, et al. · Journal of the Society for Information Display · 8
Performance Analysis of Si-Channel Nanosheet FETs with Strained SiGe Source/Drain Stressors
2020 · E. Mohapatra, T. P. Dash, et al. · Lecture notes in electrical engineering · 8
A Fully-Customized RTL to GDS Design and Verification of Low-Power Cache Memory
2024 · Eleena Mohapatra, Sudeep Kumar Shetty, et al. · IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) · 6
Work-Function Variability impact on the performance of Vertically Stacked GAA FETs for sub-7nm Technology Node
2022 · Eleena Mohapatra, Devika Jena, et al. · IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) · 6
A Simulation Study of 2-D Electron Gas in GaN HEMT for High- Speed Applications
2021 · Devika Jena, E. Mohapatra, et al. · Devices for Integrated Circuit (DevIC) · 6
Performance Analysis of FinFET based inverter at 7nm Technology Node Using TCAD Simulation
2021 · J. Jena, S. Das, et al. · Devices for Integrated Circuit (DevIC) · 5
Stress-Engineered AlGaN/GaN High Electron Mobility Transistors Design
2021 · S. Das, E. Mohapatra, et al. · Devices for Integrated Circuit (DevIC) · 5
Performance Analysis of Sub-10nm Vertically Stacked Gate-All-Around FETs
2020 · E. Mohapatra, T. P. Dash, et al. · IEEE VLSI Device Circuit and System (VLSI DCS) · 4
Fin Shape Dependence of Electrostatics and Variability in FinFETs
2019 · J. Jena, T. P. Dash, et al. · Journal of Electronic Materials · 4
Role of Stress/Strain Mapping in Advanced CMOS Process Technology Nodes
2019 · T. P. Dash, J. Jena, et al. · Devices for Integrated Circuit (DevIC) · 4
Investigation of Work Function Variation on the Electrical Performance of sub-7nm GAA FETs
2021 · E. Mohapatra, T. P. Dash, et al. · Devices for Integrated Circuit (DevIC) · 3
Metal Grain Granularity Induced Variability in Gate-All-Around Si-Nanowire Transistors at 1nm Technology Node
2019 · T. P. Dash, S. Dey, et al. · Devices for Integrated Circuit (DevIC) · 3
Works count: 64
Citation count: 296
H-index: 10
I10-index: 10
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