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Ming-Chuen Shiau

Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters
1990 · C.-Y. Wu, M.-C. Shiau · IEEE Journal of Solid-State Circuits · 32
The signal delay in interconnection lines considering the effects of small-geometry CMOS inverters
1990 · M.-C. Shiau, C.-Y. Wu · IEEE Transactions on Circuits and Systems · 13
A new interconnection delay model considering the effects of short-channel logic gates
2003 · C.-Y. Wu, M.-C. Shiau · IEEE International Symposium on Circuits and Systems proceedings · 9
Single-Port Five-Transistor SRAM Cell with Reduced Leakage Current in Standby
2016 · Chien-Cheng Yu, Ming-Chuen Shiau · International Journal of VLSI Design & Communication Systems · 4
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Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications
1990 · Chung-Yu Wu, Ming-Chuen Shiau · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 4
Single-Port 5T SRAM Cell with Improved Write-Ability and Reduced Standby Leakage Current
2017 · Chien-Cheng Yu, Ming-Chuen Shiau · International Journal of Information and Electronics Engineering · 3
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A New Single-Port Five-Transistor SRAM Cell Design for Signal Processing Systems
2019 · Chien-Cheng Yu, Chung-Bin Wu, et al. · International Conference on Integrated Circuits and Microsystems (ICICM) · 1
Design of High Performance Single-Port 5T SRAM Cell
2016 · Chien-Cheng Yu, Ming-Chuen Shiau · IOSR Journal of Electrical and Electronics Engineering · 1
Power dissipation models and performance improvement techniques for CMOS inverters with RC line and tree interconnections
1993 · H.-C. Tang, M.-C. Shiau · IEE Proceedings G Circuits Devices and Systems · 1
Design of two-port SRAM cell with improved write operation
2023 · Ming-Hsueh Wu, Chien-Cheng Yu, et al. · International Journal of Scholarly Research in Engineering and Technology
Single-Port SRAM Cell with lower leakage current in standby mode
2023 · Ming-Hsueh Wu, Chien-Cheng Yu, et al. · International Journal of Scholarly Research in Engineering and Technology
A Two-Port SRAM Cell with Improved Write-Ability and Reduced Leakage Current for Signal Processing Applications
2019 · Chien-Cheng Yu, Ming-Chuen Shiau, et al. · IEEE International Conference on Computer and Communications (ICCC)
Two-Port SRAM Cell with Improved Write Operation
2018 · Wen-Chieh Wu, Ming-Chuen Shiau, et al. · International Journal of Information and Electronics Engineering
Five-Transistor Single-Port SRAM Bit Cell with Hight Speed and Low Standby Current
2018 · Chien-Cheng Yu, Ming-Chuen Shiau, et al. · International Journal of VLSI Design & Communication Systems
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Single-Port SRAM Cell with Reduced Voltage Supply in Writing Operation
2014 · Ming-Chuen Shiau, Chien-Cheng Yu, et al. · Lecture notes in electrical engineering
Works count: 15
Citation count: 68
H-index: 4
I10-index: 2
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