Get started
Author

Dawit Burusie Abdi

Observed names: Abdi Dawit Burusie, Abdi, Dawit, D. Abdi, Dawit Abdi, Dawit B. Abdi
Institution: IMEC
ORCID: 0000-0002-3598-8798
Observed ORCID: 0000-0002-3598-8798
OpenAlex ID: A5048531024
Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain
2014 · Dawit B. Abdi, M. Jagadesh Kumar · IEEE Journal of the Electron Devices Society · 322
PDF
In-Built N+ Pocket p-n-p-n Tunnel Field-Effect Transistor
2014 · Dawit Burusie Abdi, Mamidala Jagadesh Kumar · IEEE Electron Device Letters · 160
Dielectric modulated overlapping gate-on-drain tunnel-FET as a label-free biosensor
2015 · Dawit Burusie Abdi, M. Jagadesh Kumar · Superlattices and Microstructures · 113
Dopingless PNPN tunnel FET with improved performance: Design and analysis
2015 · Mamidala Saketh Ram, Dawit Burusie Abdi · Superlattices and Microstructures · 59
PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis
2015 · Dawit Burusie Abdi, M. Jagadesh Kumar · Superlattices and Microstructures · 38
2-D Threshold Voltage Model for the Double-Gate p-n-p-n TFET With Localized Charges
2016 · Dawit Burusie Abdi, Mamidala Jagadesh Kumar · IEEE Transactions on Electron Devices · 29
Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node
2022 · Hsiao-Hsuan Liu, Shairfe M. Salahuddin, et al. · IEEE Transactions on Electron Devices · 23
PDF
Single Grain Boundary Dopingless PNPN Tunnel FET on Recrystallized Polysilicon: Proposal and Theoretical Analysis
2015 · Mamidala Saketh Ram, Dawit Burusie Abdi · IEEE Journal of the Electron Devices Society · 20
PDF
Ultimate MRAM Scaling: Design Exploration of High-Density, High-Performance and Energy-Efficient VGSOT for Last Level Cache
2023 · M. Gupta, Y. Xiang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 19
Double-Row CFET: Design Technology Co-Optimization for Area Efficient A7 Technology Node
2024 · H. Kükner, G. Mirabelli, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 17
Single Grain Boundary Tunnel Field Effect Transistors on Recrystallized Polycrystalline Silicon: Proposal and Investigation
2014 · Mamidala Saketh Ram, Dawit Burusie Abdi · IEEE Electron Device Letters · 17
Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)
2023 · S. Mishra, V. Sankatali, et al. · IEEE International Reliability Physics Symposium proceedings · 16
PDF
STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes
2023 · F. García-Redondo, S. Rao, et al. · IEEE European Solid-State Device Research Conference (ESSDERC) · 11
Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5)
2024 · S. Mishra, B. Vermeersch, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 8
Suppressing Ambipolar Conduction Using Dual Material Gate In Tunnel-Fets Having Heavily Doped Drain
2016 · Dawit Burusie Abdi, Mamidala Jagadesh Kumar · Zenodo (CERN European Organization for Nuclear Research) · 7
Dopingless tunnel FET with a hetero-material gate: Design and analysis
2014 · M. Saketh Ram, Dawit Burusie Abdi · IEEE International Conference on Emerging Electronics (ICEE) · 7
N2 Nanosheet Pathfinding-PDK (P-PDKTM) Including Back-Side PDN
2024 · Anita Farokhnejad, Siva Satyendra Sahoo, et al. · 6
3D SRAM Macro Design in 3D Nanofabric Process Technology
2023 · Dawit Burusie Abdi, Shairfe M. Salahuddin, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 6
PDF
Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis
2021 · Mamidala Karthik Ram, Neha Tiwari, et al. · IEEE Access · 6
Performance Investigation of Single Grain Boundary Junctionless Field Effect Transistor
2016 · Mamidala Saketh Ram, Dawit Burusie Abdi · IEEE Journal of the Electron Devices Society · 6
A Novel DTCO-driven 1T1R Bitcell for sub-10ns STT-MRAM LLC Macros at N12 Node
2024 · F. García-Redondo, L. Verschueren, et al. · 5
Area-Efficient CFET Dual-port SRAM with Backside Interconnect
2024 · D. Abdi, M. Brunion, et al. · 4
Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus
2024 · Zhenlin Pei, Hsiao-Hsuan Liu, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 4
PDF
Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation
2024 · S. Mishra, B. Vermeersch, et al. · IEEE International Reliability Physics Symposium proceedings · 4
PDF
Effect of Drain Induced Barrier Enhancement on Subthreshold Swing and OFF-State Current of Short Channel MOSFETs: A TCAD Study
2021 · Mamidala Karthik Ram, Neha Tiwari, et al. · IEEE Access · 4
PDF
Works count: 34
Citation count: 921
H-index: 12
I10-index: 13
Year
Topic
Type