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Author

Hsu-Yu Kao

Observed institution: Chung Yuan Christian University
ORCID: 0000-0003-2644-0007
Observed ORCID: 0000-0003-2644-0007
OpenAlex ID: A5049102423
Hardware Implementation for Multiple Activation Functions
2019 · Chih-Hsiang Chang, Hsu-Yu Kao, et al. · IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan) · 26
Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators
2021 · Wei-Hung Lin, Hsu-Yu Kao, et al. · International SoC Design Conference · 8
An industrial design methodology for the synthesis of OCV-aware top-level clock tree
2017 · Hsu-Yu Kao, Yu Lee, et al. · International Symposium on Next-Generation Electronics · 6
A Design Framework for Hardware Approximation of Deep Neural Networks
2019 · Wei-Hung Lin, Hsu-Yu Kao, et al. · International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) · 5
Cross-Mesh Clock Network Synthesis
2023 · Wei-Kai Cheng, Zih-Ming Yeh, et al. · Electronics · 4
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Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation
2022 · Hsu-Yu Kao, Shih-Hsu Huang, et al. · Electronics · 4
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Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations
2021 · Yui-Kai Weng, Shih-Hsu Huang, et al. · Sensors · 4
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Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing
2021 · Hsu-Yu Kao, Xin-Jia Chen, et al. · Sensors · 3
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Two-Stage Multi-bit Flip-Flop Clustering with Useful Skew for Low Power
2019 · Hsu-Yu Kao, Chu-Han Hsu, et al. · International Conference on Communication Engineering and Technology (ICCET) · 3
A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations
2022 · Hsu-Yu Kao, Shih-Hsu Huang · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · 2
3D Test Wrapper Chain Optimization with I/O Cells Binding Considered
2019 · Fan-Hsuan Tang, Hsu-Yu Kao, et al. · IEEE International D Systems Integration Conference · 2
A Neural Network Compiler for Efficient Data Storage Optimization in ReRAM-Based DNN Accelerators
2025 · Hsu-Yu Kao, Liang-Ying Su, et al. · Electronics · 1
A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configuration
2022 · Bo-Xi Lai, Shih-Hsu Huang, et al. · IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan) · 1
Block-Based Compression for Reducing Indexing Cost of DNN Accelerators
2021 · Yui-Kai Weng, Shih-Hsu Huang, et al. · IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan) · 1
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers
2020 · Jui-Hung Hung, Shih-Hsu Huang, et al. · IEEE VLSI Test Symposium (VTS)
Works count: 15
Citation count: 70
H-index: 4
I10-index: 1
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