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Bhupendra Singh Reniwal

Observed names: B S Reniwal, B. S. Reniwal, B.S. Reniwal, Bhupendra Reniwal, Bhupendra S. Reniwal, Bhupendra Singh Renewal
ORCID: 0000-0002-9814-3581
Observed ORCID: 0000-0002-9814-3581
OpenAlex ID: A5050869066
Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array
2023 · Kavitha Soundrapandiyan, Santosh Kumar Vishvakarma, et al. · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · 28
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design
2018 · P. Singh, B.S. Reniwal, et al. · Integration · 24
Impact of device engineering on analog/RF performances of tunnel field effect transistors
2017 · V Vijayvargiya, B S Reniwal, et al. · Semiconductor Science and Technology · 24
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Analogue/RF performance attributes of underlap tunnel field effect transistor for low power applications
2016 · V. Vijayvargiya, B.S. Reniwal, et al. · Electronics Letters · 24
Design and Analysis of Multibit Multiply and Accumulate (MAC) unit: An Analog In-Memory Computing Approach
2023 · Swetha Ananthanarayanan, Bhupendra Singh Reniwal, et al. · International Conference on VLSI Design · 18
Design and investigation of variability aware sense amplifier for low power, high speed SRAM
2016 · B.S. Reniwal, P. Bhatia, et al. · Microelectronics Journal · 13
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM
2017 · B. S. Reniwal, P. Singh, et al. · International Conference on VLSI Design · 9
Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation
2021 · Mythrai, Pragna, et al. · International Symposium on VLSI Design and Test (VDAT) · 8
An offset-tolerant self-correcting sense amplifier for robust high speed SRAM
2015 · Praneet Bhatia, B. S. Reniwal, et al. · International Symposium on VLSI Design and Test (VDAT) · 8
Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity
2015 · S.K. Vishvakarma, B.S. Reniwal, et al. · IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) · 6
Design of high speed DDR SDRAM controller with less logic utilization
2014 · Pooran Singh, Bhupendra Reniwal, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 5
In-Memory Encryption using XOR-based Feistel Cipher in SRAM Array
2024 · Kavitha S, B. S. Reniwal · IEEE International Symposium on Circuits and Systems proceedings · 4
Novel PVT Resilient Low-Power Dynamic XOR/XNOR Design Using Variable Threshold MOS for IoT Applications
2023 · Arjun Singh Yadav, Bhupendra Singh Reniwal, et al. · IETE Journal of Research · 4
Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application
2023 · Mohd Sakib Ansari S, Kavitha S, et al. · International Conference on VLSI Design · 4
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM
2018 · Bhupendra Singh Reniwal, Vikas Vijayvargiya, et al. · Circuits Systems and Signal Processing · 4
Ultra-Fast Current Mode Sense Amplifier for Small $$I_{\mathrm{CELL}}$$ I CELL SRAM in FinFET with Improved Offset Tolerance
2015 · Bhupendra Singh Reniwal, Vikas Vijayvargiya, et al. · Circuits Systems and Signal Processing · 4
A Reliable, Process-Sensitive-Tolerant Hybrid Sense Amplifier for Ultralow Power SRAM
2013 · B.S. Reniwal, S. K. Vishvakarma · International Journal of Electronics and Electrical Engineering · 4
Highly Accurate and Energy Efficient Convolutional Spiking Neural Network for Traffic Sign Recognition
2025 · Chetali Yadav, Bhupendra Singh Reniwal · IEEE Access · 2
EASI-CiM: Event-driven Asynchronous Stream-based Image classifier with Compute-in-Memory kernels
2024 · R. Sreekumar, Minseong Park, et al. · International Symposium on Quality Electronic Design (ISQED) · 2
Energy Efficient and Reliable Embedded Nanoscale SRAM Design
2023 · Bhupendra Singh Reniwal, Pooran Singh, et al. · CRC Press eBooks · 2
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array
2022 · S Kavitha, S. K. Vishvakarma, et al. · Communications in computer and information science · 2
Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications
2019 · Ankur Beohar, Gopal Raut, et al. · Communications in computer and information science · 2
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small I cell SRAM Using FinFET
2015 · Bhupendra Singh Reniwal, Vikas Vijayvargiya, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 2
Spatially Invariant Convolutional Spiking Neural Network For Resource-Constrained IoT Devices
2025 · Chetali Yadav, Bhupendra Singh Reniwal · Circuits Systems and Signal Processing · 1
Approach Toward In-Memory Computing-Based Hamming Code Implementation For Error Correction and Detection
2024 · Vani Marani, A. B. Chandrahas Reddy, et al. · Lecture notes in electrical engineering · 1
Works count: 43
Citation count: 208
H-index: 8
I10-index: 6
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