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Author

Renzo Andri

Observed name: Andri, Renzo
Institution: ETH Zurich
ORCID: 0000-0002-8776-5158
Observed ORCID: 0000-0002-8776-5158
OpenAlex ID: A5050957615
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration
2017 · Renzo Andri, Lukas Cavigelli, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 249
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YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights
2016 · Renzo Andri, Lukas Cavigelli, et al. · IEEE Computer Society Annual Symposium on VLSI · 219
Stretchable and Conformable Oxide Thin‐Film Electronics
2015 · Niko Münzenrieder, Giuseppe Cantarella, et al. · Advanced Electronic Materials · 100
A “New Ara” for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
2022 · Matteo Perotti, Matheus Cavalcante, et al. · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · 89
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InfiniTime: Multi-sensor wearable bracelet with human body harvesting
2016 · Michele Magno, Davide Brunelli, et al. · Sustainable Computing Informatics and Systems · 84
Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor
2024 · Matteo Perotti, Matheus Cavalcante, et al. · IEEE Transactions on Computers · 48
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XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks
2018 · Bahou, Andrawes A., Karunaratne, Geethan, et al. · arXiv (Cornell University) · 48
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Sound event detection with binary neural networks on tightly power-constrained IoT devices
2020 · Gianmarco Cerutti, Renzo Andri, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 46
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XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks
2018 · Andrawes Al Bahou, Geethan Karunaratne, et al. · IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) · 45
Accelerated Visual Context Classification on a Low-Power Smartwatch
2016 · Francesco Conti, Daniele Palossi, et al. · IEEE Transactions on Human-Machine Systems · 42
Sub-mW Keyword Spotting on an MCU: Analog Binary Feature Extraction and Binary Neural Networks
2022 · Gianmarco Cerutti, Lukas Cavigelli, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 31
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MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory
2023 · Samuel Riedel, Matheus Cavalcante, et al. · IEEE Transactions on Computers · 30
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Flex-SFU: Accelerating DNN Activation Functions by Non-Uniform Piecewise Approximation
2023 · Enrico Reggiani, Renzo Andri, et al. · ACM/IEEE Design Automation Conference (DAC) · 29
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ChewBaccaNN: A Flexible 223 TOPS/W BNN Accelerator
2021 · Renzo Andri, Geethan Karunaratne, et al. · IEEE International Symposium on Circuits and Systems proceedings · 24
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Hyperdrive: A Multi-Chip Systolically Scalable Binary-Weight CNN Inference Engine
2019 · Renzo Andri, Lukas Cavigelli, et al. · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · 18
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Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes
2018 · Renzo Andri, Lukas Cavigelli, et al. · IEEE Computer Society Annual Symposium on VLSI · 18
Going Further With Winograd Convolutions: Tap-Wise Quantization for Efficient Inference on 4x4 Tiles
2022 · Renzo Andri, Beatrice Bussolino, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 16
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Flex-SFU: Activation Function Acceleration With Nonuniform Piecewise Approximation
2025 · Renzo Andri, Enrico Reggiani, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 13
Extending the RISC-V ISA for Efficient RNN-based 5G Radio Resource Management
2020 · Renzo Andri, Tomas Henriksson, et al. · ACM/IEEE Design Automation Conference (DAC) · 12
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RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures
2021 · Gianna Paulin, Renzo Andri, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 11
SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC
2014 · Michael Gautschi, Michael Muehlberghuber, et al. · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · 10
Stella Nera: A Differentiable Maddness-Based Hardware Accelerator for Efficient Approximate Matrix Multiplication
2025 · Jannis Schönleber, Lukas Cavigelli, et al. · IEEE Computer Society Annual Symposium on VLSI · 6
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Empowering Data Centers for Next Generation Trusted Computing
2022 · Dhar, Aritra, Sridhara, Supraja, et al. · arXiv (Cornell University) · 6
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Ultra-Low Power Context Recognition Fusing Sensor Data from an Energy-Neutral Smart Watch
2016 · Michele Magno, Lukas Cavigelli, et al. · Lecture notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering · 5
FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators
2025 · Chi Zhang, Luca Colagrande, et al. · IEEE Computer Society Annual Symposium on VLSI · 4
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Works count: 42
Citation count: 1,227
H-index: 16
I10-index: 21
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