Author

Kan Shi

Observed name: Shi, Kan

Institutions: Chinese Academy of Sciences, Institute of Computing Technology, University of Chinese Academy of Sciences

Observed institutions: Chinese Academy of Sciences, Institute of Computing Technology, University of Chinese Academy of Sciences

ORCID: 0000-0002-8461-0820

Observed ORCID: 0000-0002-8461-0820

OpenAlex ID: A5055045167

Towards Developing High Performance RISC-V Processors Using Agile Methodology

2022 · Yinan Xu, Zihao Yu, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 111

ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration

2023 · Kan Shi, Shuoxiang Xu, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 20

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Functional Verification for Agile Processor Development: A Case for Workflow Integration

2023 · Yi-Nan Xu, Zi-Hao Yu, et al. · Journal of Computer Science and Technology · 6

Latency Insensitivity Testing for Dataflow HLS Designs

2025 · Jianyi Cheng, Lianghui Wang, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 2

Hassert: Hardware Assertion-Based Verification Framework with FPGA Acceleration

2024 · Ziqing Zhang, Weijie Weng, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 2

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TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification

2026 · Yang Zhong, Haoran Wu, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 1

Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration

2025 · Zijian Jiang, Keran Zheng, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 1

Democratizing and Accelerating Hardware Verification with Software-Native Optimization

2026 · Yunlong Xie, Zhicheng Yao, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings

Orion: Automated Verification of Randomized Dynamic Schedules for Dataflow HLS

2026 · Lianghui Wang, Zijian Jiang, et al. · International Symposium of Electronics Design Automation (ISEDA)

Reducing SQED Duplicate Mode Via Processor-Level Abstraction

2026 · Yufeng Li, Linze Li, et al. · International Symposium of Electronics Design Automation (ISEDA)

From Indiscriminate to Targeted: Functionally Critical Signal-Driven Assertion Generation using LLMs for Efficient RTL Verification

2026 · Wang, Yonghao, Lyu, Hongqin, et al. · arXiv (Cornell University)

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TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification

2025 · Zhong, Yang, Wu, Haoran, et al. · arXiv (Cornell University)

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Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration

2025 · Shuoxiang Xu, Zijian Jiang, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

Works count: 14

Citation count: 143

H-index: 3

I10-index: 2