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Prakash Ramrakhyani

Observed name: Ramrakhyani, Prakash
ORCID: 0009-0001-0774-1501
Observed ORCID: 0009-0001-0774-1501
OpenAlex ID: A5057505004
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories
2018 · Gururaj Saileshwar, Prashant J. Nair, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 101
Shredder
2020 · Fatemehsadat Mireshghallah, Mohammadkazem Taram, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 92
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SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories
2018 · Gururaj Saileshwar, Prashant J. Nair, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 88
A case for dynamic pipeline scaling
2002 · Jinson Koppanalil, Prakash Ramrakhyani, et al. · International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · 41
BBB: Simplifying Persistent Programming using Battery-Backed Buffers
2021 · Mohammad Alshboul, Prakash Ramrakhyani, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 38
A case for dynamic pipeline scaling
2002 · Jinson Koppanalil, Prakash Ramrakhyani, et al. · International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · 12
Accurate system-level performance modeling and workload characterization for mobile internet devices
2008 · Mitchell Hayenga, Chander Sudanthi, et al. · Memory Performance: Dealing With Applications, Systems And Architecture · 11
SESAME: Software defined Enclaves to Secure Inference Accelerators with Multi-tenant Execution
2020 · Banerjee, Sarbartha, Ramrakhyani, Prakash, et al. · arXiv (Cornell University) · 9
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Triton: Software-Defined Threat Model for Secure Multi-Tenant ML Inference Accelerators
2023 · Sarbartha Banerjee, Shijia Wei, et al. · Hardware and Architectural Support for Security and Privacy · 7
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Dynamic Pipeline Scaling
2003 · Prakash Ramrakhyani · NCSU Libraries Repository (North Carolina State University Libraries) · 7
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SecDDR: Enabling Low-Cost Secure Memories by Protecting the DDR Interface
2023 · Ali Fakhrzadehgan, Prakash Ramrakhyani, et al. · International Conference on Dependable Systems & Networks/Proceedings · 4
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Reducing Data Movement and Energy in Multilevel Cache Hierarchies without Losing Performance: Can you have it all?
2019 · Jiajun Wang, Prakash Ramrakhyani, et al. · International Conference on Parallel Architectures and Compilation Techniques (PACT) · 4
Shredder: Learning Noise to Protect Privacy with Partial DNN Inference on the Edge.
2019 · Fatemehsadat Mireshghallah, Mohammadkazem Taram, et al. · arXiv (Cornell University) · 4
Bandwidth Utilization Side-Channel on ML Inference Accelerators
2021 · Banerjee, Sarbartha, Wei, Shijia, et al. · arXiv (Cornell University) · 3
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Obsidian: Cooperative State-Space Exploration for Performant Inference on Secure ML Accelerators
2024 · Banerjee, Sarbartha, Wei, Shijia, et al. · arXiv (Cornell University) · 1
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Tail Victims in Termination Timing Channel Defenses Beyond Cryptographic Kernels
2024 · Shijia Wei, Austin Harris, et al. · International Symposium on Secure and Private Execution Environment Design (SEED)
Works count: 18
Citation count: 422
H-index: 8
I10-index: 7
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