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Süleyman Sırrı Demirsoy

Observed names: Demirsoy, Suleyman, S.S. Demirsoy, Suleyman Demirsoy, Suleyman S. Demirsoy, Suleyman Sirri Demirsoy
Observed institutions: University of Geneva, National Technical University of Athens, Altera (United States), Altera (United Kingdom), Intel (United Kingdom), University of Westminster
ORCID: 0009-0006-5881-7883
Observed ORCID: 0009-0006-5881-7883
OpenAlex ID: A5058306867
Efficient implementation of digital filters using novel reconfigurable multiplier blocks
2005 · S.S. Demirsoy, I. Kale, et al. · Asilomar Conference on Signals, Systems and Computers (ACSSC) · 48
Power analysis of multiplier blocks
2003 · S.S. Demirsoy, A.G. Dempster, et al. · IEEE International Symposium on Circuits and Systems proceedings · 38
Transition analysis on FPGA for multiplier-block based FIR filter structures
2002 · S.S. Demirsoy, A. Dempster, et al. · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 36
Reconfigurable Multiplier Blocks: Structures, Algorithm and Applications
2007 · Süleyman Sırrı Demirsoy, Izzet Kale, et al. · Circuits Systems and Signal Processing · 28
Design guidelines for reconfigurable multiplier blocks
2003 · S.S. Demirsoy, A.G. Dempster, et al. · IEEE International Symposium on Circuits and Systems proceedings · 25
hls4ml: A Flexible, Open Source Platform for Deep Learning Acceleration on Reconfigurable Hardware
2026 · Jan-Frederik Schulte, Benjamin Ramhorst, et al. · ACM Transactions on Reconfigurable Technology and Systems · 18
hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware
2025 · Schulte, Jan-Frederik, Ramhorst, Benjamin, et al. · Bristol Research (University of Bristol) · 14
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Cholesky decomposition using fused datapath synthesis
2009 · Suleyman S. Demirsoy, Martin Langhammer · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 14
Synthesis of Reconfigurable Multiplier Blocks: Part II-Algorithm
2005 · S.S. Demirsoy, I. Kale, et al. · IEEE International Symposium on Circuits and Systems proceedings · 13
Fast & Strong: The Case of Compressed String Dictionaries on Modern CPUs
2019 · Robert Lasch, Ismail Oukid, et al. · International Workshop on Data Management on New Hardware (DaMoN) · 12
Synthesis of Reconfigurable Multiplier Blocks: Part I-Fundamentals
2005 · S.S. Demirsoy, I. Kale, et al. · IEEE International Symposium on Circuits and Systems proceedings · 12
Power consumption behaviour of multiplier block algorithms
2003 · S.S. Demirsoy, A.G. Dempster, et al. · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · 9
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Reconfigurable implementation of recursive DCT kernels for reduced quantization noise
2003 · S.S. Demirsoy, R. Beck, et al. · IEEE International Symposium on Circuits and Systems proceedings · 8
Faster & strong: string dictionary compression using sampling and fast vectorized decompression
2020 · Robert Lasch, Ismail Oukid, et al. · The VLDB Journal · 6
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Efficient Fpga Implementation Of An Adaptive Iq-Imbalance Corrector For Communication Receivers Using Reduced Range Multipliers
2005 · Cetin, Ediz, Demirsoy, Suleyman, et al. · 6
Novel recursive-DCT implementations: a comparative study
2002 · S.S. Demirsoy, R. Beck, et al. · IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS) · 6
Accelerating In-memory Database Functionality with FPGAs
2024 · Jordan Leggett, John McGlone, et al. · ACM Transactions on Reconfigurable Technology and Systems · 4
Accelerating re-pair compression using FPGAs
2020 · Robert Lasch, Suleyman S. Demirsoy, et al. · International Workshop on Data Management on New Hardware (DaMoN) · 4
Optimizing LLM inference for FPGAs
2025 · Jorge R De Freitas, Jose G. F. Coutinho, et al. · IEEE International Conference on ASIC (ASICON) · 2
A Combined Streaming FPGA Architecture for Client-Side CKKS Encoding and Encryption
2026 · Kurina, Joseph, Pasca, Bogdan, et al. · arXiv (Cornell University)
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hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware
2025 · Schulte, Jan-Frederik, Ramhorst, Benjamin, et al. · Repository for Publications and Research Data (ETH Zurich)
Evolution of the oneAPI Backend for hls4ml
2025 · Jovan Mitrevski, Altera, UK, et al. · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information)
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New Recursive Dct Implementations With Goertzel Filters
2014 · Suleyman Sirri Demirsoy, Robert Beck, et al. · International Journal of Computing
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SoC framework for FPGA: A case study of LTE PUSCH receiver
2009 · Suleyman S. Demirsoy, Kellie Marks · IEEE International SOC Conference (SOCC)
Session MA5: Programmable and reconfigurable architectures
2008 · Suleyman Demirsoy · Asilomar Conference on Signals, Systems and Computers (ACSSC)
Works count: 32
Citation count: 307
H-index: 11
I10-index: 11
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