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Rupam Sardar
Observed names:
Rupam Sardar -,
Rupam Sardar1
Institutions:
Budge Budge Institute of Technology,
Maulana Abul Kalam Azad University of Technology, West Bengal
Observed institutions:
Budge Budge Institute of Technology,
Maulana Abul Kalam Azad University of Technology, West Bengal
ORCID:
0000-0002-2382-5051
Observed ORCID:
0000-0002-2382-5051
OpenAlex ID:
A5058385978
Prediction of Humidity using Multi Linear Perceptron and Support Vector Machine North Twenty-four Parganas , West Bengal
2024
·
Rupam Sardar
, Sudip Ghosh
, et al.
·
INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT
·
1
PDF
Prediction of Air Pressure using Support Vector Machine Compare with Multi Layer Perception Model in an Area of North Twenty-four Parganas, West Bengal
2024
·
Rupam Sardar -
, Sudip Ghosh -
, et al.
·
International Journal For Multidisciplinary Research
·
1
Artificial Neural Network Design for CMOS NAND Gate Using Sigmoid Function
2023
·
Rupam Sardar
, Arkapravo Nandi
, et al.
·
Lecture notes in electrical engineering
·
1
Design of EX-OR Gate with ANN Using Sigmoid and ReLU Functions for Artificial Intelligence Applications in Python
2023
·
Rupam Sardar
, Arkapravo Nandi
, et al.
·
Lecture notes in networks and systems
·
1
Instruction Level Parallelism and Memory Synchronization
2024
·
Rupam Sardar
·
INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT
PDF
Cache Memory Organization and Virtual Memory
2024
·
Rupam Sardar
·
INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT
PDF
Basic Computer Architecture and Quantitative Techniques in Computer Design Instruction Pipeline ,Arithmetic Pipeline, Hazards ,Exception and Interrupts
2024
·
Rupam Sardar
·
INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT
PDF
2:1 Multiplexer, 1:2 De-multiplexer,2:4 Decoder and 4:2 Encoder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output
2024
·
Rupam Sardar
·
INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT
PDF
Full Adder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output
2024
·
Rupam Sardar1
, Sudip Ghosh2
, et al.
·
INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT
PDF
Designing Half-Adder with CMOS Technology using Artificial Neural Network with Verilog Implementation
2024
·
Rupam Sardar
, Sudip Ghosh
, et al.
·
INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT
PDF
Multi-linear Regression Model for Weather Prediction in North 24 Parganas, IN
2024
·
Rupam Sardar
, Debashis De
, et al.
·
Lecture notes in networks and systems
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Works count:
11
Citation count:
4
H-index:
1
I10-index:
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