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Jayashree Saxena

A case study of ir-drop in structured at-speed testing
2004 · J. Saxena, K.M. Butler, et al. · IEEE International Test Conference (ITC) · 400
Minimizing power consumption in scan testing: pattern generation and DFT techniques
2005 · K.M. Butler, J. Saxena, et al. · IEEE International Test Conference (ITC) · 273
An analysis of power reduction techniques in scan testing
2002 · J. Saxena, K.M. Butler, et al. · IEEE International Test Conference (ITC) · 163
Scan-based transition fault testing - implementation and low cost test challenges
2003 · J. Saxena, K.M. Butler, et al. · IEEE International Test Conference (ITC) · 130
A design for testability scheme to reduce test application time in full scan
2003 · D.K. Pradhan, J. Saxena · IEEE VLSI Test Symposium (VTS) · 55
A method to derive compact test sets for path delay faults in combinational circuits
2002 · J. Saxena, D.K. Pradhan · IEEE International Test Conference (ITC) · 32
On applying non-classical defect models to automated diagnosis
2002 · J. Saxena, K.M. Butler, et al. · IEEE International Test Conference (ITC) · 29
An empirical study on the effects of test type ordering on overall test efficiency
2002 · K.M. Butler, J. Saxena · IEEE International Test Conference (ITC) · 23
Bridging fault diagnosis in the absence of physical information
2002 · D.B. Lavo, B. Chess, et al. · IEEE International Test Conference (ITC) · 22
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis
2002 · Z. Stanojevic, H. Balachandran, et al. · IEEE International Test Conference (ITC) · 15
Automated diagnosis in testing and failure analysis
1997 · K.M. Butler, K. Johnson, et al. · IEEE Design & Test of Computers · 15
Low Power Test for Nanometer System-on-Chips (SoCs)
2008 · Srivaths Ravi, Rubin Parekhji, et al. · Journal of Low Power Electronics · 14
Modeling Test Escape Rate as a Function of Multiple Coverages
2008 · K.M. Butler, J.M. Carulli, et al. · IEEE International Test Conference (ITC) · 11
Signature analysis under a delay fault model
2003 · J. Saxena, D.K. Pradhan · European Design Automation Conference · 6
Multidimensional Test Escape Rate Modeling
2009 · K.M. Butler, J.M. Carulli, et al. · IEEE Design & Test of Computers · 4
A novel scheme to reduce test application time in circuits with full scan
1995 · D.K. Pradhan, J. Saxena · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 4
Design for testability of asynchronous sequential circuits
2002 · J. Saxena, D.K. Pradhan · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 2
Integrating automated diagnosis into the testing and failure analysis operations
2002 · K.M. Butler, K. Johnson, et al. · IEEE International Test Conference (ITC) · 2
IC diagnosis: preventing wars and war stories
2002 · J. Saxena · IEEE International Test Conference (ITC) · 1
Schemes to reduce test application time in digital circuit testing
1993 · J. Saxena · Scholarworks (University of Massachusetts Amherst)
Works count: 21
Citation count: 1,201
H-index: 12
I10-index: 13
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