Get started
Author

Jinming Lu

Observed names: J. Lu, Lu, Jinming
ORCID: 0000-0002-7134-6514
Observed ORCIDs: 0000-0002-7134-6514, 0009-0007-0192-3703
OpenAlex ID: A5059107361
E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory
2019 · Meiqi Wang, Zhisheng Wang, et al. · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · 78
Evaluations on Deep Neural Networks Training Using Posit Number System
2020 · Jinming Lu, Chao Fang, et al. · IEEE Transactions on Computers · 72
ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization
2022 · Jinming Lu, Chao Ni, et al. · IEEE Transactions on Neural Networks and Learning Systems · 32
Training Deep Neural Networks Using Posit Number System
2019 · Jinming Lu, Siyuan Lu, et al. · IEEE International System-on-Chip Conference (SOCC) · 22
PDF
An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization
2023 · Haikuo Shao, Jinming Lu, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 21
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration
2022 · Jinming Lu, Jian Huang, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 13
WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd
2023 · Jinming Lu, Hui Wang, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 10
A Reconfigurable DNN Training Accelerator on FPGA
2020 · Jinming Lu, Jun Lin, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 9
A Hardware-Oriented and Memory-Efficient Method for CTC Decoding
2019 · Siyuan Lu, Jinming Lu, et al. · IEEE Access · 9
PDF
An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd
2023 · Hui Wang, Jinming Lu, et al. · IEEE Computer Society Annual Symposium on VLSI · 8
An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training
2021 · Haikuo Shao, Jinming Lu, et al. · IEEE Computer Society Annual Symposium on VLSI · 6
LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks
2020 · Chao Ni, Jinming Lu, et al. · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · 6
A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA
2021 · Tongtong Yin, Wendong Mao, et al. · IEEE Computer Society Annual Symposium on VLSI · 4
FLAT-LLM: Fine-grained Low-rank Activation Space Transformation for Large Language Model Compression
2026 · Jiayi Tian, Ryan Solgi, et al. · Findings of the Association for Computational Linguistics: EACL · 3
PDF
An Efficient CNN Training Accelerator Leveraging Transposable Block Sparsity
2022 · Mingyang Xu, Jinming Lu, et al. · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · 3
A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding
2019 · Siyuan Lu, Jinming Lu, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 3
An Efficient Hardware Architecture for DNN Training by Exploiting Triple Sparsity
2022 · Jian Huang, Jinming Lu, et al. · IEEE International Symposium on Circuits and Systems proceedings · 2
High-performance neural network training on a computational cluster
2004 · J. Lu, D. Goldman, et al. · International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia) · 2
CDM-QTA: Quantized Training Acceleration for Efficient LoRA Fine-Tuning of Diffusion Model
2025 · Jinming Lu, Minghao She, et al. · IEEE International Symposium on Circuits and Systems proceedings · 1
PDF
SATurbine: A Multicore Transformer Accelerator With Gated Broadcast for Efficient Dynamic Sparse Attention
2026 · Wentao Xu, Yuxuan Zhang, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HoloLUT: An Efficient LUT-Based Engine via Holistic Data Processing for Low-bit LLM Inference
2026 · Hui Wang, Weize Ma, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI)
ZOAF: Towards Efficient Zeroth-Order Optimization for Analog/RF Circuit Design
2026 · Tan, Liyan, Zhao, Yequan, et al. · arXiv (Cornell University)
PDF
Tensor-Compressed and Fully-Quantized Training of Neural PDE Solvers
2025 · Lu, Jinming, Tian, Jiayi, et al. · arXiv (Cornell University)
PDF
Works count: 24
Citation count: 304
H-index: 9
I10-index: 7
Year
Topic
Type