Get started
Author

Michael Raitza

Institution: Barkhausen Institut
ORCID: 0000-0003-2370-4054
Observed ORCID: 0000-0003-2370-4054
OpenAlex ID: A5060193481
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors
2018 · Shubham Rai, Jens Trommer, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 122
Exploiting transistor-level reconfiguration to optimize combinational circuits
2017 · Michael Raitza, Akash Kumar, et al. · Design, Automation, and Test in Europe · 69
PDF
Reconfigurable Nanowire Transistors with Multiple Independent Gates for Efficient and Programmable Combinational Circuits
2016 · Jens Trommer, André Heinzig, et al. · Design, Automation, and Test in Europe · 55
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs
2018 · Shubham Rai, Ansh Rupani, et al. · Design, Automation, and Test in Europe · 34
Technology mapping flow for emerging reconfigurable silicon nanowire transistors
2018 · Shubham Rai, Michael Raitza, et al. · Design, Automation, and Test in Europe · 28
DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies
2020 · Shubham Rai, Michael Raitza, et al. · Design, Automation, and Test in Europe · 23
A Hardware/Software Stack for Heterogeneous Systems
2017 · Jeronimo Castrillon, Jochen Frohlich, et al. · IEEE Transactions on Multi-Scale Computing Systems · 22
Quantitative Characterization of Reconfigurable Transistor Logic Gates
2020 · Michael Raitza, Steffen Marcker, et al. · IEEE Access · 12
PDF
Formal Analysis of Camouflaged Reconfigurable Circuits
2023 · Steffen Märcker, Michael Raitza, et al. · IEEE Interregional NEWCAS Conference (NEWCAS) · 11
RAW 2014: Random Number Generators on FPGAs
2015 · Michael Raitza, Markus Vogt, et al. · ACM Transactions on Reconfigurable Technology and Systems · 9
Influence of operating conditions on ring oscillator-based entropy sources in FPGAs
2012 · Christian Hochberger, Changgong Li, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 7
Towards GCC-based automatic soft-core customization
2012 · Gerald Hempel, Christian Hochberger, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 6
Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach
2022 · Michael Raitza, Steffen Marcker, et al. · Design, Automation, and Test in Europe · 4
Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput
2021 · Abhiroop Bhattacharjee, Shubham Rai, et al. · IFIP/IEEE International Conference on Very Large Scale Integration · 4
A Secure-by-Design Hardware/Operating System as a Substrate for Trustworthy Computing
2025 · Sebastian Haas, Christopher Dunkel, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 3
END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator
2022 · Shubham Rai, Nishant Gupta, et al. · IFIP advances in information and communication technology · 3
AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs
2021 · Najdet Charaf, Christoph Tietz, et al. · International Conference on Field-Programmable Technology (FPT) · 3
Influence of Magnetic Fields and X-Radiation on Ring Oscillators in FPGAs
2014 · Michael Raitza, Markus Vogt, et al. · IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum · 2
An Architectural Approach for the Secure Integration of Hardware Accelerators into a Trustworthy MPSoC Platform
2025 · Sebastian Haas, Mattis Hasler, et al. · IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) · 1
The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware
2016 · Marcus Völp, Sascha Klüppelholz, et al. · BOA (University of Milano-Bicocca) · 1
PDF
Secure AI Runtime System Based on the M3 Platform
2025 · Mattis Hasler, Michael Raitza, et al. · Asilomar Conference on Signals, Systems and Computers (ACSSC)
Tutorial: How to Use Model Checking to Analyze Circuits at the Transistor Level
2023 · Michael Raitza, Steffen Märcker · International Conference on Hardware/Software Codesign and System Synthesis
PDF
Session details: Special Session: Hardware Security through Reconfigurability: Attacks, Defenses, and Challenges
2022 · Michael Raitza · International Conference on Computer Aided Design
(Invited) High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits
2016 · Walter M. Weber, André Heinzig, et al. · ECS Meeting Abstracts
Works count: 24
Citation count: 419
H-index: 9
I10-index: 9
Year
Topic
Type