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Author

Tianyu Liao

Institution: Tsinghua University
Observed institution: Tsinghua University
ORCID: 0009-0008-2114-4990
Observed ORCID: 0009-0008-2114-4990
OpenAlex ID: A5061243521
Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm CMOS
2023 · Guodong Yin, Yiming Chen, et al. · IEEE Journal of Solid-State Circuits · 23
DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level
2025 · Tianyi Yu, Tianyu Liao, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 8
A 28nm 166.9 TOPS/W x Mb/mm2 DRAM-Free QLC Compute-in-ROM Macro Supporting High Task-Level Inference Energy Efficiency for Tiny AI Edge Devices
2024 · Ling-An Cheong, Chen Wang, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 7
DCiROM: A High-Density Fully-Digital Compute-in-Read-Only-Memory Macro for Energy-Efficient Task-Level DNN Inference
2025 · Tianyi Yu, Tianyu Liao, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 5
Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices
2023 · Juejian Wu, Tianyu Liao, et al. · 3
Kung-Fu: An Energy-Efficient Compute-In-Memory Approach for Neural Network Inference Using Multi-Level Binary Computing Fusion
2025 · Tianyu Liao, Yiming Chen, et al. · IEEE International Symposium on Circuits and Systems proceedings · 2
SPIDER: A Sparsity-Aware High-Density Compute-in-ROM Architecture for Large-Scale Neural Networks On-Chip Deployment
2025 · Tianyu Liao, Tianyi Yu, et al.
Works count: 7
Citation count: 48
H-index: 4
I10-index: 1
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