Get started
Author

Archana Singhal

ORCID: 0009-0008-4217-0258
Observed ORCID: 0009-0008-4217-0258
OpenAlex ID: A5063748632
A Novel 571.78 MHz–11.07 GHz Tuning Range Differential Ring Oscillator Application in a PLL Frequency Synthesizer with 895 ns Lock Time
2024 · Archana Singhal, Riyaz Ahmad, et al. · Circuits Systems and Signal Processing · 9
Optimization of performance parameters of differential ring oscillator using Taguchi DoE and Pareto ANOVA techniques for fast-setting PLL frequency synthesizer
2025 · Archana Singhal, Jyoti Sharma, et al. · Analog Integrated Circuits and Signal Processing · 8
An efficient race-free dynamic MCML design for multistage applications
2025 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · Analog Integrated Circuits and Signal Processing · 4
Design and Analysis of Fast Settling Wideband PLL Using a Novel Low Mismatch Current Charge Pump
2024 · Archana Singhal, Jyoti Sharma, et al. · IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems · 4
Design and Optimization of a Symmetrical Phase-Frequency Detector (SPFD) Through Statistical Techniques
2025 · Jyoti Sharma, Archana Singhal, et al. · Circuits Systems and Signal Processing · 2
Design and optimization of a low-power dynamic MCML-based phase-frequency detector using Taguchi DoE and ANOVA for frequency synthesizers with fast-locking of 0.5 μs
2026 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · AEU - International Journal of Electronics and Communications · 1
Design and Analysis of PVT Tolerant and Fast-Settling Wideband CP-PLL Frequency Synthesizer
2025 · Archana Singhal, Dheeraj Singh Rajput, et al. · International Conference on Device Intelligence, Computing and Communication Technologies (DICCT) · 1
Optimization of Performance of Novel Quad Tail Cell Dynamic PFSCL Design Using Statistical Techniques for Low-Power Three-Input Logic Applications
2026 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · Circuits Systems and Signal Processing
Correction: Optimization of novel DPTL-PFD design for fast-settling PLL frequency synthesizer using Taguchi–ANOVA
2026 · Archana Singhal, Jyoti Sharma, et al. · Analog Integrated Circuits and Signal Processing
PDF
Improved Race-Free Cascaded Dynamic PFSCL Technique for Multistage Applications
2026 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · Circuits Systems and Signal Processing
A Low-Phase Noise, Low-Power PFD Circuit Using GDI and Pass Transistor Logic with PVT tolerance
2026 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · International Conference on Consumer Electronics
Optimization of novel DPTL-PFD design for fast-settling PLL frequency synthesizer using Taguchi–ANOVA
2026 · Archana Singhal, Jyoti Sharma, et al. · Analog Integrated Circuits and Signal Processing
Design and Optimization of a PTL Based PFD (PPFD) Circuit using Taguchi DoE and Anova Methods for High Speed and Wide Range Frequency Synthesizer
2026 · Jyoti Sharma, Archana Singhal, et al. · SSRN Electronic Journal
Power-Efficient and High-Speed Dynamic MCML XOR Gate Using Triple-Tail Cells Architecture
2026 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · Lecture notes in electrical engineering
Design and Analysis of a GHz PLL Using GDI and Pass Transistor Based PFD with a Lock Time of 520 ns
2025 · Dheeraj Singh Rajput, Bharat Choudhary, et al. · IEEE International Symposium on Smart Electronic Systems (iSES)
Design of Wideband, Low Phase Noise 3-Stage and 5-Stage Differential Ring VCOs for Wireless Communication Systems
2025 · Archana Singhal, Dheeraj Singh Rajput, et al. · IEEE International Symposium on Smart Electronic Systems (iSES)
Design and Evaluation of a Power Efficient Phase-Frequency Detector with PVT Tolerance in 45 nm CMOS Technology
2024 · Jyoti Sharma, Archana Singhal, et al. · IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems
Works count: 17
Citation count: 29
H-index: 4
I10-index:
Year
Topic
Type