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Ziaul Choudhury
Observed name:
Choudhury, Ziaul
Institution:
Vignan's Foundation for Science, Technology & Research
Observed institutions:
Siemens (Germany),
Vignan's Foundation for Science, Technology & Research,
International Institute of Information Technology, Hyderabad
ORCID:
0000-0001-9019-0239
Observed ORCID:
0000-0001-9019-0239
OpenAlex ID:
A5064037179
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism
2022
·
Ziaul Choudhury
, Shashwat Shrivastava
, et al.
·
ACM Transactions on Architecture and Code Optimization
·
21
PDF
A Unified Programmable Edge Matrix Processor for Deep Neural Networks and Matrix Algebra
2022
·
Biji George
, Om Ji Omer
, et al.
·
ACM Transactions on Embedded Computing Systems
·
13
PDF
FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation
2020
·
Shashwat Shrivastava
, Ziaul Choudhury
, et al.
·
International Conference on Field Programmable Logic and Applications (FPL)
·
13
Accelerating Local Laplacian Filters on FPGAs
2020
·
Shashwat Khandelwal
, Ziaul Choudhury
, et al.
·
International Conference on Field Programmable Logic and Applications (FPL)
·
5
PDF
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler
2023
·
Ziaul Choudhury
, Anish Gulati
, et al.
·
ACM Transactions on Architecture and Code Optimization
·
4
PDF
Bitwidth customization in image processing pipelines using interval analysis and SMT solvers
2020
·
Suresh Purini
, Vinamra Benara
, et al.
·
4
A Hybrid CPU+GPU Working-Set Dictionary
2016
·
Ziaul Choudhury
, Suresh Purini
, et al.
·
International Symposium on Parallel and Distributed Computing
·
3
Accuracy Configurable FPGA Implementation of Harris Corner Detection
2022
·
Shivani Maurya
, Ziaul Choudhury
, et al.
·
IEEE Computer Society Annual Symposium on VLSI
·
1
Heterogeneous (CPU+GPU) Working-set Hash Tables
2016
·
Ziaul Choudhury
, Suresh Purini
·
1
Discrete algebraic ring signatures on elliptic curves for privacy-preserving blockchain transaction authentication
2026
·
Ziaul Choudhury
, Ruth Kalangi
, et al.
·
Journal of Discrete Mathematical Sciences and Cryptography
PDF
Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths
2018
·
Benara, Vinamra
, Choudhury, Ziaul
, et al.
·
arXiv (Cornell University)
PDF
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Works count:
12
Citation count:
65
H-index:
4
I10-index:
3
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