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Dolphin Abessolo‐Bidzo

Observed names: ABESSOLO BIDZO, Dolphin, D. Abessolo-Bidzo, Dolphin Abessolo, Dolphin Abessolo Bidzo, Dolphin Abessolo-Bidzo
Institution: NXP (Germany)
OpenAlex ID: A5064377986
CDM Simulation Based on Tester, Package and Full Integrated Circuit Modeling: Case Study
2012 · Dolphin Abessolo-Bidzo, Theo Smedes, et al. · IEEE Transactions on Electron Devices · 18
Isolating failing sites in IC packages using time domain reflectometry: Case studies
2005 · D. Abessolo-Bidzo, P. Poirier, et al. · Microelectronics Reliability · 13
A Study of HBM and CDM Layout Simulations Tools
2018 · Dolphin Abessolo-Bidzo, Richard Derikx, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 4
Wear out effects in ESD characterization and testing
2015 · Theo Smedes, Dolphin Abessolo-Bidzo · Electrical Overstress/Electrostatic Discharge Symposium · 4
A study of the effect of remote CDM clamps in integrated circuits
2015 · Dolphin Abessolo-Bidzo, Theo Smedes, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 4
Signal-power integrity and EMI analysis for singlechip and multi-chip-module applications
2013 · Sidina Wane, Aykut Erdem, et al. · International Conference on Electromagnetics in Advanced Applications (ICEAA) · 4
Failure localization in IC packages using time domain reflectometry: technique limitations and possible improvements
2005 · D. Abessolo-Bidzo, P. Poirier, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 4
Circuit under pad active bipolar ESD clamp for RF applications
2017 · Dolphin Abessolo-Bidzo, Eric Thomas · Electrical Overstress/Electrostatic Discharge Symposium · 2
Window effects in HBM and TLP testing
2017 · Theo Smedes, Wolfgang Scheucher, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 2
Predictive CDM simulation approach based on tester, package and full integrated circuit modeling
2011 · Dolphin Abessolo-Bidzo, Theo Smedes, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 2
ESD protection circuit for a sub-1dB noise figure LNA in a SiGe:C BiCMOS technology
2013 · Dolphin Abessolo-Bidzo, Rob Krosschell, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 1
Improved test structure for on‐wafer microwave characterization of components
2010 · Philippe Descamps, Dolphin Abessolo‐Bidzo, et al. · Microwave and Optical Technology Letters · 1
Removing S-parameters on-wafer measurements parasitic elements using time domain gating: Application to transmission lines
2006 · Dolphin Abessolo-Bidzo, Patrick Poirier, et al. · Asia-Pacific Microwave Conference (APMC) · 1
Modeling of ESD Diodes in the CDM Time Domain
2026 · Weiying Li, Yijun Liu, et al. · Annual EOS/ESD Symposium (EOS/ESD)
Case Study of a Miscorrelation Between CDM Testing and CC-TLP Characterization of Multi-GHz RF Pins
2025 · Dolphin Abessolo-Bidzo, Johannes Weber, et al. · Annual EOS/ESD Symposium (EOS/ESD)
A Silicon BJT Active ESD Clamp Design in a Silicon Germanium HBT BiCMOS Technology
2021 · Dolphin Abessolo-Bidzo, Peter Magnee, et al. · Annual EOS/ESD Symposium (EOS/ESD)
Charged Device Model (CDM) and Capacitive Coupled Transmission Line Pulsing (CC-TLP) Stress Severity Study on RF IC's
2020 · Dolphin Abessolo-Bidzo, Johannes Weber, et al. · Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft)
Méthodologies de test pour la caractérisation radiofréquence et hyperfréquence de composants microélectroniques avancés et systèmes intégrés en vue de leur modélisation et du contrôle non destructif
2007 · Dolphin Abessolo Bidzo
Works count: 19
Citation count: 60
H-index: 4
I10-index: 2
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