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Author

Madhura Purnaprajna

Observed names: M. Purnaprajna, Purnaprajna, Madhura
Institution: PES University
Observed institutions: University of Alberta, PES University, Paderborn University, Instituto de Telecomunicações, Heinz Nixdorf Stiftung, École Polytechnique Fédérale de Lausanne, Halmstad University, University of Coimbra, Amrita Vishwa Vidyapeetham
ORCID: 0000-0003-4995-6233
Observed ORCID: 0000-0003-4995-6233
OpenAlex ID: A5064989404
Recurrent Neural Networks: An Embedded Computing Perspective
2020 · Nesma M. Rezk, Madhura Purnaprajna, et al. · IEEE Access · 151
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A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures
2021 · Oscar Ferraz, Srinivasan Subramaniyan, et al. · IEEE Communications Surveys & Tutorials · 86
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Genetic algorithms for hardware–software partitioning and optimal resource allocation
2006 · Madhura Purnaprajna, Marek Reformat, et al. · Journal of Systems Architecture · 44
Review of Electrostatic Force Calculation Methods and Their Acceleration in Molecular Dynamics Packages Using Graphics Processors
2022 · Anu George, Sandip Mondal, et al. · ACS Omega · 31
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case
2012 · G. Falcao, M. Owaida, et al. · IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · 20
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Making wide-issue VLIW processors viable on FPGAs
2012 · Madhura Purnaprajna, Paolo Ienne · ACM Transactions on Architecture and Code Optimization · 16
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Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions
2015 · Meena Belwal, Madhura Purnaprajna, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 14
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography
2008 · Madhura Purnaprajna, Christoph Puttmann, et al. · Design, Automation, and Test in Europe · 13
CoIn: Accelerated CNN Co-Inference through data partitioning on heterogeneous devices
2020 · K. Vanishree, Anu George, et al. · International Conference on Advanced Computing and Communication Systems (ICACCS) · 12
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs
2015 · Muhsen Owaida, Gabriel Falcao, et al. · ACM Transactions on Embedded Computing Systems · 12
Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance
2009 · Mario Porrmann, Madhura Purnaprajna, et al. · NASA/ESA Conference on Adaptive Hardware and Systems (AHS) · 11
ASIC implementation of a high speed WGNG for communication channel emulation [white Gaussian noise generator]
2004 · E. Fung, K. Leung, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 10
Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis
2021 · Remya Ramakrishnan, Aditya K V Dev, et al. · International Conference on VLSI Design · 8
Compiler-driven reconfiguration of multiprocessors
2007 · Michael Hussmann, Michael Thies, et al. · PUB – Publications at Bielefeld University (Bielefeld University) · 8
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Asic Implementation of a High Speed Wgng for Communication Channel Emulation
2004 · Edmund Fung, Kaston Leung, et al. · 7
MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication
2022 · M. R. Ashuthosh, Santosh Krishna, et al. · International Conference on VLSI Design · 5
k-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational Genomics
2019 · Simmi M Bose, Varsha S Lalapura, et al. · International Conference on VLSI Design · 5
Work in Progress: Performance Modeling for Data Distribution in Heterogeneous Computing Systems
2018 · K. Vanishree, Madhura Purnaprajna · International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · 5
TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs
2018 · Sahu Sai Vikram, Vibha Pant, et al. · International Conference on VLSI Design · 5
Shadow And-Inverter Cones
2013 · Hadi Parandeh-Afshar, Grace Zgheib, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 5
A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers
2013 · Madhura Purnaprajna, Paolo Ienne · IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · 4
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only)
2013 · Hadi Parandeh-Afshar, Grace Zgheib, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 4
Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders
2022 · Srinivasan Subramaniyan, Oscar Ferraz, et al. · IEEE Design and Test · 3
Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs
2020 · Srinivasan Subramaniyan, Oscar Ferraz, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 3
Gbit/s Non-Binary LDPC Decoders: High-Throughput using High-Level Specifications
2020 · Oscar Ferraz, Srinivasan Subramaniyan, et al. · IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · 3
Works count: 46
Citation count: 501
H-index: 11
I10-index: 12
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